diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 23d095d1a6..299190f364 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -45,6 +45,13 @@ config BR2_RISCV_ISA_RVV
 	bool "Vector Instructions (V)"
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
 
+config BR2_RISCV_ISA_EXTRA
+	string "Append extra RISC-V ISA extensions"
+	help
+	  Extra ISA extensions to append to the ISA extensions string.
+	  They are underscore-separated.  For example,
+	  "zba_zbb_zvl256b".
+
 choice
 	prompt "Target Architecture Size"
 	default BR2_RISCV_64
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index ee5c434b97..e47666eadd 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -39,4 +39,9 @@ ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
 endif
 
+ARCH_RISV_ISA_EXTRA = $(call qstrip, $(BR2_RISCV_ISA_EXTRA))
+ifneq ($(ARCH_RISV_ISA_EXTRA),)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_$(ARCH_RISV_ISA_EXTRA)
+endif
+
 endif