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configs/andes_ae350_45: enable RISC-V atomic extension

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Let's select the RVA option as Andes 45-series CPUs support IMAFDC
extensions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Yu Chien Peter Lin
2023-08-15 13:43:27 +08:00
committed by Thomas Petazzoni
parent be5e4a1708
commit f5573b8a04
1 changed files with 1 additions and 0 deletions
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configs/andes_ae350_45_defconfig
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@@ -1,6 +1,7 @@
BR2_riscv=y
BR2_riscv_custom=y
BR2_RISCV_ISA_RVM=y
BR2_RISCV_ISA_RVA=y
BR2_RISCV_ISA_RVF=y
BR2_RISCV_ISA_RVD=y
BR2_RISCV_ISA_RVC=y