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https://gitlab.com/buildroot.org/buildroot.git
synced 2026-08-01 13:18:36 -09:00
166bfd3e66
Adds a new user-configurable string to arch/Config.in.riscv, and in arch/arch.mk.riscv appends it to GCC_TARGET_ARCH. This enables custom extensions/combinations to be easily configured. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Jesse Taube <Mr.Bossman075@gmail.com> [Arnout: - fix check-package warnings - introduce ARCH_RISV_ISA_EXTRA to simplify stripping of quotes ] Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
48 lines
1.2 KiB
Plaintext
48 lines
1.2 KiB
Plaintext
#
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# Configure the GCC_TARGET_ARCH variable and append the
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# appropriate RISC-V ISA extensions.
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#
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ifeq ($(BR2_riscv),y)
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ifeq ($(BR2_RISCV_64),y)
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GCC_TARGET_ARCH := rv64i
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else
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GCC_TARGET_ARCH := rv32i
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endif
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ifeq ($(BR2_RISCV_ISA_RVM),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
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endif
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ifeq ($(BR2_RISCV_ISA_RVA),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
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endif
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ifeq ($(BR2_RISCV_ISA_RVF),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
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endif
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ifeq ($(BR2_RISCV_ISA_RVD),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
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endif
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ifeq ($(BR2_RISCV_ISA_RVC),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
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endif
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ifeq ($(BR2_RISCV_ISA_RVV),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
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endif
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# Starting from gcc 12.x, csr and fence instructions have been
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# separated from the base I instruction set, and special -march
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# suffixes are needed to enable their support. In Buildroot, we assume
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# all RISC-V cores that support Linux implement those instructions, so
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# we unconditionally enable those extensions.
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ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
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endif
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ARCH_RISV_ISA_EXTRA = $(call qstrip, $(BR2_RISCV_ISA_EXTRA))
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ifneq ($(ARCH_RISV_ISA_EXTRA),)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_$(ARCH_RISV_ISA_EXTRA)
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endif
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endif
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