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The URL https://github.com/riscv/riscv-openocd is now redirecting to: https://github.com/riscv-collab/riscv-openocd This commit updates the URL to this new location. Signed-off-by: Julien Olivain <ju.o@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
32 lines
1001 B
Plaintext
32 lines
1001 B
Plaintext
Linux on Spike RISC-V ISA simulator
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===================================
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This configuration provides a minimal working setup to run a Linux
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kernel in the Spike RISC-V ISA simulator.
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The Spike ISA simulator can be an interresting alternative to Qemu, in
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some specific cases. For example: simulating new instructions (see [1]),
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simulating riscv-openocd/gdb debug sessions (see [2], [3]), or
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generating an accurate per-instruction log of execution (see
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riscv-isa-sim spike -l option)...
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To run Buildroot Linux in Spike, use the commands:
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make spike_riscv64_defconfig
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make
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./board/spike/riscv64/start.sh
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The boot is made with the standard RISC-V OpenSBI boot loader. In
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order to keep the simulation simple, the rootfs is passed as an initrd
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ramfs.
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[1].
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https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
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[2].
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https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-gdb
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[3].
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https://github.com/riscv-collab/riscv-openocd
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