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Merge remote-tracking branch 'origin/patch'

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Ryan Kurtz
2026-07-23 05:19:42 -04:00
parent 67e67d02d9 0bffbabbbb
commit 1b419420d3
5 changed files with 203 additions and 103 deletions
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1
Ghidra/Processors/x86/certification.manifest
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@@ -14,6 +14,7 @@ data/languages/cet.sinc||GHIDRA||||END|
data/languages/clwb.sinc||GHIDRA||||END| data/languages/clwb.sinc||GHIDRA||||END|
data/languages/cmpccxadd.sinc||GHIDRA||||END| data/languages/cmpccxadd.sinc||GHIDRA||||END|
data/languages/fma.sinc||GHIDRA||||END| data/languages/fma.sinc||GHIDRA||||END|
data/languages/gfni.sinc||GHIDRA||||END|
data/languages/ia.sinc||GHIDRA||||END| data/languages/ia.sinc||GHIDRA||||END|
data/languages/lockable.sinc||GHIDRA||||END| data/languages/lockable.sinc||GHIDRA||||END|
data/languages/lzcnt.sinc||GHIDRA||||END| data/languages/lzcnt.sinc||GHIDRA||||END|

96
Ghidra/Processors/x86/data/languages/avx512.sinc
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@@ -13680,102 +13680,6 @@ define pcodeop vaesenclast_vaes ;
ZmmReg1 = vaesenclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 ); ZmmReg1 = vaesenclast_vaes( evexV5_ZmmReg, ZmmReg2_m512 );
} }
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56498
define pcodeop vgf2p8affineinvqb_avx512vl ;
:VGF2P8AFFINEINVQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmResult = vgf2p8affineinvqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56501
:VGF2P8AFFINEINVQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmResult = vgf2p8affineinvqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56504
define pcodeop vgf2p8affineinvqb_avx512f ;
:VGF2P8AFFINEINVQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
ZmmResult = vgf2p8affineinvqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56642
define pcodeop vgf2p8affineqb_avx512vl ;
:VGF2P8AFFINEQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmResult = vgf2p8affineqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56645
:VGF2P8AFFINEQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmResult = vgf2p8affineqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56648
define pcodeop vgf2p8affineqb_avx512f ;
:VGF2P8AFFINEQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCE; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
ZmmResult = vgf2p8affineqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56754
define pcodeop vgf2p8mulb_avx512vl ;
:VGF2P8MULB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
XmmResult = vgf2p8mulb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56757
:VGF2P8MULB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
YmmResult = vgf2p8mulb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56760
define pcodeop vgf2p8mulb_avx512f ;
:VGF2P8MULB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
ZmmResult = vgf2p8mulb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
# PCLMULQDQ 4-242 PAGE 1362 LINE 76037 # PCLMULQDQ 4-242 PAGE 1362 LINE 76037
define pcodeop vpclmulqdq_vpclmulqdq ; define pcodeop vpclmulqdq_vpclmulqdq ;
:VPCLMULQDQ XmmReg1, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 :VPCLMULQDQ XmmReg1, evexV5_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_XmmReg; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8

193
Ghidra/Processors/x86/data/languages/gfni.sinc Normal file
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@@ -0,0 +1,193 @@
#66 0F3A CF /r /ib
#GF2P8AFFINEINVQB xmm1,
#xmm2/m128, imm8 A V/V
#GFNI Computes inverse affine transformation in the finite field GF(2^8).
define pcodeop gf2p8affineinvqb;
:GF2P8AFFINEINVQB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = gf2p8affineinvqb(XmmReg2_m128, XmmReg1, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.128.66.0F3A.W1 CF /r /ib
#VGF2P8AFFINEINVQB xmm1, xmm2,
#xmm3/m128, imm8 B V/V
#AVX GFNI Computes inverse affine transformation in the finite field GF(2^8).
define pcodeop vgf2p8affineinvqb_avx;
:VGF2P8AFFINEINVQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = vgf2p8affineinvqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.256.66.0F3A.W1 CF /r /ib
#VGF2P8AFFINEINVQB ymm1, ymm2,
#ymm3/m256, imm8 B V/V AVX
#GFNI Computes inverse affine transformation in the finite field GF(2^8).
:VGF2P8AFFINEINVQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmReg1 = vgf2p8affineinvqb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
ZmmReg1 = zext(YmmReg1);
}
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56498
define pcodeop vgf2p8affineinvqb_avx512vl ;
:VGF2P8AFFINEINVQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmResult = vgf2p8affineinvqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56501
:VGF2P8AFFINEINVQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmResult = vgf2p8affineinvqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8AFFINEINVQB 3-476 PAGE 1046 LINE 56504
define pcodeop vgf2p8affineinvqb_avx512f ;
:VGF2P8AFFINEINVQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
ZmmResult = vgf2p8affineinvqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
#66 0F3A CE /r /ib
#GF2P8AFFINEQB xmm1, xmm2/m128, imm8 A V/V GFNI
#Computes affine transformation in the finite field GF(2^8).
define pcodeop gf2p8affineqb;
:GF2P8AFFINEQB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x3A; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = gf2p8affineqb(XmmReg2_m128, XmmReg1, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.128.66.0F3A.W1 CE /r /ib
#VGF2P8AFFINEQB xmm1, xmm2, xmm3/m128, imm8 B V/V AVX
#GFNI Computes affine transformation in the finite field GF(2^8).
define pcodeop vgf2p8affineqb_avx;
:VGF2P8AFFINEQB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = vgf2p8affineqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.256.66.0F3A.W1 CE /r /ib
#VGF2P8AFFINEQB ymm1, ymm2, ymm3/m256, imm8 B V/V AVX
#GFNI Computes affine transformation in the finite field GF(2^8).
:VGF2P8AFFINEQB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmReg1 = vgf2p8affineqb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
ZmmReg1 = zext(YmmReg1);
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56642
define pcodeop vgf2p8affineqb_avx512vl ;
:VGF2P8AFFINEQB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask8 & evexV5_XmmReg; byte=0xCE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmResult = vgf2p8affineqb_avx512vl( evexV5_XmmReg, XmmReg2_m128_m64bcst, imm8:1 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56645
:VGF2P8AFFINEQB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask8 & evexV5_YmmReg; byte=0xCE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmResult = vgf2p8affineqb_avx512vl( evexV5_YmmReg, YmmReg2_m256_m64bcst, imm8:1 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8AFFINEQB 3-479 PAGE 1049 LINE 56648
define pcodeop vgf2p8affineqb_avx512f ;
:VGF2P8AFFINEQB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCE; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
ZmmResult = vgf2p8affineqb_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}
#66 0F38 CF /r
#GF2P8MULB xmm1, xmm2/m128 A V/V
#GFNI Multiplies elements in the finite field GF(2^8).
define pcodeop gf2p8mulb;
:GF2P8MULB XmmReg1, XmmReg2_m128, imm8 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x38; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = gf2p8mulb(XmmReg2_m128, XmmReg1, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.128.66.0F38.W0 CF /r
#VGF2P8MULB xmm1, xmm2, xmm3/m128 B V/V AVX
#GFNI Multiplies elements in the finite field GF(2^8).
define pcodeop vgf2p8mulb_avx;
:VGF2P8MULB XmmReg1, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
XmmReg1 = vgf2p8affineqb_avx( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 );
ZmmReg1 = zext(XmmReg1);
}
#VEX.256.66.0F38.W0 CF /r
#VGF2P8MULB ymm1, ymm2, ymm3/m256 B V/V AVX
#GFNI Multiplies elements in the finite field GF(2^8).
:VGF2P8MULB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8
[ evexD8Type = 0; evexTType = 0; ] # (TupleType Full)
{
YmmReg1 = vgf2p8mulb_avx( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 );
ZmmReg1 = zext(YmmReg1);
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56754
define pcodeop vgf2p8mulb_avx512vl ;
:VGF2P8MULB XmmReg1 XmmOpMask8, evexV5_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8 & evexV5_XmmReg; byte=0xCF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
XmmResult = vgf2p8mulb_avx512vl( evexV5_XmmReg, XmmReg2_m128 );
XmmMask = XmmReg1;
build XmmOpMask8;
ZmmReg1 = zext(XmmResult);
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56757
:VGF2P8MULB YmmReg1 YmmOpMask8, evexV5_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8 & evexV5_YmmReg; byte=0xCF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
YmmResult = vgf2p8mulb_avx512vl( evexV5_YmmReg, YmmReg2_m256 );
YmmMask = YmmReg1;
build YmmOpMask8;
ZmmReg1 = zext(YmmResult);
}
# GF2P8MULB 3-481 PAGE 1051 LINE 56760
define pcodeop vgf2p8mulb_avx512f ;
:VGF2P8MULB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask8 & evexV5_ZmmReg; byte=0xCF; ZmmReg1 ... & ZmmReg2_m512
[ evexD8Type = 1; evexTType = 0; ] # (TupleType Full Mem)
{
ZmmResult = vgf2p8mulb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 );
ZmmMask = ZmmReg1;
build ZmmOpMask8;
ZmmReg1 = ZmmResult;
}

15
Ghidra/Processors/x86/data/languages/ia.sinc
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@@ -9065,14 +9065,15 @@ define pcodeop psllw;
:PSLLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = psllw(mmxreg2, imm8:8); } :PSLLW mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x71; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { mmxreg2 = psllw(mmxreg2, imm8:8); }
:PSLLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxreg ... & m64 ... { :PSLLD mmxreg, m64 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxreg ... & m64 ... {
local m:8 = m64; local count = m64;
mmxreg[0,32] = mmxreg[0,32] << m[0,32]; mmxreg[0,32] = mmxreg[0,32] << count;
mmxreg[32,32] = mmxreg[32,32] << m[32,32]; mmxreg[32,32] = mmxreg[32,32] << count;
} }
:PSLLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxmod = 3 & mmxreg1 & mmxreg2 { :PSLLD mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF2; mmxmod = 3 & mmxreg1 & mmxreg2 {
mmxreg1[0,32] = mmxreg1[0,32] << mmxreg2[0,32]; local count = mmxreg2;
mmxreg1[32,32] = mmxreg1[32,32] << mmxreg2[32,32]; mmxreg1[0,32] = mmxreg1[0,32] << count;
mmxreg1[32,32] = mmxreg1[32,32] << count;
} }
:PSLLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 { :PSLLD mmxreg2, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0x72; mod = 0b11 & reg_opcode=6 & mmxreg2; imm8 {
@@ -9090,7 +9091,7 @@ define pcodeop psllw;
:PSLLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; XmmReg ... & m128 ... { :PSLLD XmmReg, m128 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; XmmReg ... & m128 ... {
local m:16 = m128; local m:16 = m128;
local count:4 = m[0,32]; local count:8 = m(0);
XmmReg[0,32] = XmmReg[0,32] << count; XmmReg[0,32] = XmmReg[0,32] << count;
XmmReg[32,32] = XmmReg[32,32] << count; XmmReg[32,32] = XmmReg[32,32] << count;
XmmReg[64,32] = XmmReg[64,32] << count; XmmReg[64,32] = XmmReg[64,32] << count;
@@ -9098,7 +9099,7 @@ define pcodeop psllw;
} }
:PSLLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; xmmmod = 3 & XmmReg1 & XmmReg2 { :PSLLD XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0xF2; xmmmod = 3 & XmmReg1 & XmmReg2 {
local count:4 = XmmReg2[0,32]; local count = XmmReg2[0,64];
XmmReg1[0,32] = XmmReg1[0,32] << count; XmmReg1[0,32] = XmmReg1[0,32] << count;
XmmReg1[32,32] = XmmReg1[32,32] << count; XmmReg1[32,32] = XmmReg1[32,32] << count;
XmmReg1[64,32] = XmmReg1[64,32] << count; XmmReg1[64,32] = XmmReg1[64,32] << count;

1
Ghidra/Processors/x86/data/languages/x86.slaspec
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@@ -7,6 +7,7 @@ with : lockprefx=0 {
@include "avx2_manual.sinc" @include "avx2_manual.sinc"
@include "avx512.sinc" @include "avx512.sinc"
@include "avx512_manual.sinc" @include "avx512_manual.sinc"
@include "gfni.sinc"
@include "adx.sinc" @include "adx.sinc"
@include "clwb.sinc" @include "clwb.sinc"
@include "pclmulqdq.sinc" @include "pclmulqdq.sinc"