diff --git a/Ghidra/Processors/PowerPC/data/languages/altivec.sinc b/Ghidra/Processors/PowerPC/data/languages/altivec.sinc index 2acecf52b0..1e5a190da0 100644 --- a/Ghidra/Processors/PowerPC/data/languages/altivec.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/altivec.sinc @@ -1850,3 +1850,12 @@ define pcodeop altv300_71; :vsrv vrD,vrA,vrB is OP=4 & vrD & vrA & vrB & XOP_0_10=1796 { vrD = altv300_71(vrA,vrB); } + +# vmsumudm 000100 ..... ..... ..... ..... 100011 +# Vector Multiply Sum Unsigned Doubleword Modulo +:vmsumudm vrD,vrA,vrB,vrC is OP=4 & vrD & vrA & vrB & vrC & XOP_0_5=35 { + local temp:16 = zext(vrC); + temp = temp + zext(vrA[ 0,32])*zext(vrB[ 0,32]); + temp = temp + zext(vrA[32,32])*zext(vrB[32,32]); + vrD = temp; +} diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc index e7f9580713..cbcfd2bd13 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc @@ -47,7 +47,7 @@ define register offset=0x500 size=1 [ fp_fx fp_fex fp_vx fp_ox fp_cc0 fp_cc1 fp_cc2 fp_cc3 fp_reserve1 fp_vxsoft fp_vxsqrt fp_vxcvi fp_ve fp_oe fp_ue fp_ze - fp_xe fp_ni fp_rn0 fp_rn1 ]; + fp_xe fp_ni fp_rn0 fp_rn1 fp_drn ]; define register offset = 0x700 size =$(REGISTER_SIZE) [MSR]; define register offset = 0x720 size=$(REGISTER_SIZE) [RESERVE_ADDRESS]; @@ -676,6 +676,7 @@ define token instr(32) CT=(21,25) CT2=(21,24) CX=(3,3) + CYex=(9,10) D0=(6,15) signed D1=(16,20) D2=(0,0) @@ -690,6 +691,7 @@ define token instr(32) DM2=(2,2) DQ=(4,15) DQs=(4,15) signed + DRM=(11,13) DS=(2,15) DSs=(2,15) signed DX=(16,20) @@ -713,6 +715,7 @@ define token instr(32) fS=(21,25) fT=(21,25) IMM=(11,15) + IMM4=(11,14) EVUIMM=(11,15) BU_UIMM=(16,20) @@ -724,6 +727,7 @@ define token instr(32) L= (21,22) L2=(21,21) L16=(16,17) + LBIT=(16,16) LEV=(5,11) LI=(2,25) signed LK=(0,0) @@ -743,6 +747,7 @@ define token instr(32) RA=(16,20) RB=(11,15) + RM=(11,12) RS=(21,25) RT=(21,25) R0=(0,0) @@ -1780,8 +1785,7 @@ macro storeRegisterPartial(reg, ea, sa) { ea = ea + 4; } - -macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, + macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { D = zext(a31) & 1; D=D|(zext(a0)&1)<<31; D=D|(zext(a1)&1)<<30; D=D|(zext(a2)&1)<<29; D=D|(zext(a3)&1)<<28; @@ -1793,6 +1797,7 @@ macro packbits( D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, D=D|(zext(a24)&1)<<7; D=D|(zext(a25)&1)<<6; D=D|(zext(a26)&1)<<5; D=D|(zext(a27)&1)<<4; D=D|(zext(a28)&1)<<3; D=D|(zext(a29)&1)<<2; D=D|(zext(a30)&1)<<1; } + macro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16,a17,a18,a19,a20,a21,a22,a23,a24,a25,a26,a27,a28,a29,a30,a31) { @@ -1803,13 +1808,15 @@ macro unpackbits(D,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15, a16=(D&0x8000)!=0; a17=(D&0x4000)!=0; a18=(D&0x2000)!=0; a19=(D&0x1000)!=0; a20=(D&0x800)!=0; a21=(D&0x400)!=0; a22=(D&0x200)!=0; a23=(D&0x100)!=0; a24=(D&0x80)!=0; a25=(D&0x40)!=0; a26=(D&0x20)!=0; a27=(D&0x10)!=0; - a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; } + a28=(D&0x8)!=0; a29=(D&0x4)!=0; a30=(D&0x2)!=0; a31=(D&0x1)!=0; + } macro packFPSCR(tmp) { packbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, fp_ux, fp_zx, fp_xx, fp_vxsnan, fp_vxisi, fp_vxidi, fp_vxzdz, fp_vximz, fp_vxvc, fp_fr, fp_fi, fp_c, fp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, fp_xe, fp_ni, fp_rn0, fp_rn1); + tmp[32,3] = fp_drn; } macro unpackFPSCR(tmp) { unpackbits(tmp, fp_fx, fp_fex, fp_vx, fp_ox, @@ -1819,7 +1826,8 @@ macro unpackFPSCR(tmp) { fp_cc0, fp_cc1, fp_cc2, fp_cc3, fp_reserve1, fp_vxsoft, fp_vxsqrt, fp_vxcvi, fp_ve, fp_oe, fp_ue, fp_ze, - fp_xe, fp_ni, fp_rn0, fp_rn1); + fp_xe, fp_ni, fp_rn0, fp_rn1); + fp_drn = tmp[32,3]; } diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc index fd17f4fdc7..736c7cce31 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_instructions.sinc @@ -2401,17 +2401,17 @@ define pcodeop lswxOp; #mffs fD 0xfc 00 04 8e :mffs fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - fD = zext(tmp); + fD = tmp; } #mffs. fD 0xfc 00 04 8f :mffs. fD is $(NOTVLE) & OP=63 & fD & BITS_11_20=0 & XOP_1_10=583 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - fD = zext(tmp); + fD = tmp; cr1flags(); } @@ -2489,69 +2489,113 @@ define pcodeop lswxOp; #mtfsf 10,fr0 0xfc 00 05 8e :mtfsf FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; - mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; - mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; - mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; - mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; - mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; - mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; - mask7:4 = zext((FM7:1 == 1)* 0xf); + mask0:8 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:8 = zext((FM7:1 == 1)* 0xf); - mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; - tmp1:4 = fB:4; - tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + tmp1:8 = fB; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); + unpackFPSCR(tmp2); +} + +:mtfsf FM,fB,1 is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=1 & fB & XOP_1_10=711 & Rc=0 +{ + tmp:8 = 0; + packFPSCR(tmp); + + mask0:8 = zext((FM0:1 == 1)* 0xf) << 60; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 56; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 52; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 48; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 44; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 40; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 36; + mask7:8 = zext((FM7:1 == 1)* 0xf) << 32; + + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + + tmp1:8 = fB:8; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); unpackFPSCR(tmp2); } #mtfsf. 10,fr0 0xfc 00 05 8f :mtfsf. FM,fB is $(NOTVLE) & OP=63 & BIT_25=0 & FM & FM0 & FM1 & FM2 & FM3 & FM4 & FM5 & FM6 & FM7 & BIT_16=0 & fB & XOP_1_10=711 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); - mask0:4 = zext((FM0:1 == 1)* 0xf) << 28; - mask1:4 = zext((FM1:1 == 1)* 0xf) << 24; - mask2:4 = zext((FM2:1 == 1)* 0xf) << 20; - mask3:4 = zext((FM3:1 == 1)* 0xf) << 16; - mask4:4 = zext((FM4:1 == 1)* 0xf) << 12; - mask5:4 = zext((FM5:1 == 1)* 0xf) << 8; - mask6:4 = zext((FM6:1 == 1)* 0xf) << 4; - mask7:4 = zext((FM7:1 == 1)* 0xf); + mask0:8 = zext((FM0:1 == 1)* 0xf) << 28; + mask1:8 = zext((FM1:1 == 1)* 0xf) << 24; + mask2:8 = zext((FM2:1 == 1)* 0xf) << 20; + mask3:8 = zext((FM3:1 == 1)* 0xf) << 16; + mask4:8 = zext((FM4:1 == 1)* 0xf) << 12; + mask5:8 = zext((FM5:1 == 1)* 0xf) << 8; + mask6:8 = zext((FM6:1 == 1)* 0xf) << 4; + mask7:8 = zext((FM7:1 == 1)* 0xf); - mask:4 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; + mask:8 = mask0 | mask1 | mask2 | mask3 | mask4 | mask5 | mask6 | mask7; - tmp1:4 = fB:4; - tmp2:4 = (tmp & ~mask) | (tmp1 & mask); + tmp1:8 = fB:8; + tmp2:8 = (tmp & ~mask) | (tmp1 & mask); unpackFPSCR(tmp2); cr1flags(); } #mtfsfi 10,3 0xfc 00 01 0c -:mtfsfi crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=0 +:mtfsfi crfD,IMM4 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=0 & XOP_1_10=134 & Rc=0 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); shift:1 = 28-(crfD*4); - mask:4 = 0xf << shift; - tmp1:4 = IMM << shift; - tmp2:4 = (tmp & ~mask) | tmp1; + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); +} + +:mtfsfi crfD,IMM4,1 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=1 & XOP_1_10=134 & Rc=0 +{ + tmp:8 = 0; + packFPSCR(tmp); + shift:1 = 60-(crfD*4); + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; unpackFPSCR(tmp2); } #mtfsfi. 10,3 0xfc 00 01 0d -:mtfsfi. crfD,IMM is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM & BIT_11=0 & XOP_1_10=134 & Rc=1 +:mtfsfi. crfD,IMM4 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=0 & XOP_1_10=134 & Rc=1 { - tmp:4 = 0; + tmp:8 = 0; packFPSCR(tmp); shift:1 = 28-(crfD*4); - mask:4 = 0xf << shift; - tmp1:4 = IMM << shift; - tmp2:4 = (tmp & ~mask) | tmp1; + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; + unpackFPSCR(tmp2); + cr1flags(); +} + +:mtfsfi. crfD,IMM4,1 is $(NOTVLE) & OP=63 & crfD & BITS_16_22=0 & IMM4 & BIT_11=1 & XOP_1_10=134 & Rc=1 +{ + tmp:8 = 0; + packFPSCR(tmp); + shift:1 = 60-(crfD*4); + mask:8 = 0xf << shift; + tmp1:8 = IMM4 << shift; + tmp2:8 = (tmp & ~mask) | tmp1; unpackFPSCR(tmp2); cr1flags(); } @@ -3116,7 +3160,10 @@ CRM_val: crmval is CRM [crmval = CRM+0;] {export *[const]:1 crmval;} #sc 0x44 00 00 02 :sc LEV is $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=1 & BIT_0=0 { - syscall(); + local lev:1 = LEV; + SRR0 = inst_next; + SRR1 = MSR; + syscall(lev); } #slbia 0x7C 00 03 E4 diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index fe36db64b7..027d3feaf3 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1131,7 +1131,7 @@ define pcodeop MessageClear; # binutils: a2.d: 548: 7c 00 51 9c msgsnd r10 # binutils: e500mc.d: 18: 7c 00 71 9c msgsnd r14 define pcodeop MessageSend; -:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(); } +:msgsnd B is OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=206 & BIT_0=0 { MessageSend(B); } # ======================================================================= @@ -2441,21 +2441,21 @@ define pcodeop InstructionCacheBlockLockSetX; } :cnttzw A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=0 { - A = countTrailingZeros(S); + A = countTrailingZeros(S); } :cnttzw. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=1 { - A = countTrailingZeros(S); - cr0flags(A); + A = countTrailingZeros(S); + cr0flags(A); } :cnttzd A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=0 { - A = countTrailingZeros(S); + A = countTrailingZeros(S); } :cnttzd. A,S is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=570 & Rc=1 { - A = countTrailingZeros(S); - cr0flags(A); + A = countTrailingZeros(S); + cr0flags(A); } :copy RA_OR_ZERO,B,L2 is $(NOTVLE) & OP=31 & BITS_22_25=0 & BIT_0=0 & XOP_1_10=774 & RA_OR_ZERO & B & L2 { @@ -2580,6 +2580,23 @@ define pcodeop InstructionCacheBlockLockSetX; setCrBit(cr0, 2, 1); } +define pcodeop returnFromSyscallVectored; +:rfscv is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=82 & BIT_0=0 +{ + MSR = returnFromSyscallVectored(MSR, CTR); + local ra = LR; + return[ra]; +} + +define pcodeop syscallVectored; +:scv LEV is $(NOTVLE) & OP=17 & BITS_12_25=0 & LEV & BITS_2_4=0 & BIT_1=0 & BIT_0=1 +{ + local lev:1 = LEV; + LR = inst_next; + CTR = MSR; + syscallVectored(lev); +} + :setb D,BFA is $(NOTVLE) & OP=31 & BITS_11_17=0 & BIT_0=0 & XOP_1_10=128 & D & BFA { tmpcr:8 = 1 << (8 * BFA:1); tmpr0:1 = (BFA & 0x8) != 0; @@ -2614,3 +2631,104 @@ define pcodeop InstructionCacheBlockLockSetX; :wait WC is $(NOTVLE) & OP=31 & BITS_23_25=0 & BITS_11_20=0 & BIT_0=0 & XOP_1_10=30 & WC { waitT(WC:1); } + +##### +# v3.0B/C instructions added + +# note: CY=0 is the only one currently defined. 1-3 are reserved +# addex 011111 ..... ..... ..... ..101 01010/ +:addex D, A, B, CYex is $(NOTVLE) & OP=31 & D & A & B & CYex & BIT_9=0 & BIT_10=0 & XOP_1_8=170 & BIT_0=0 { + local sum:$(REGISTER_SIZE) = A + B; + local carryOut = carry(A,B) | carry(sum, zext(xer_ov)); + D = sum + zext(xer_ov); + xer_ov = carryOut; +} + +@ifdef BIT_64 +# mffscdrn 111111 ..... 10100 ..... 10010 00111/ +define pcodeop mffscdrn; +:mffscdrn fT, fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=20 & fB & XOP_1_10=583 & BIT_0=0 { + local tmp:8 = 0; + local _tmpDRM:1 = fB[29,3]; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_drn = _tmpDRM; +} + +# mffscdrni 111111 ..... 10101 //... 10010 00111/ +:mffscdrni fT, DRM is $(NOTVLE) & OP=63 & fT & BITS_16_20=20 & BITS_13_15=0 & DRM & XOP_1_10=583 & BIT_0=0 { + local tmp:8 = 0; + local _tmpDRM:1 = DRM; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_drn = _tmpDRM; +} + +# mffsce 111111 ..... 00001 ///// 10010 00111/ +:mffsce fT is $(NOTVLE) & OP=63 & fT & BITS_16_20=1 & BITS_11_15=0 & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp; + fp_ve=0; + fp_oe=0; + fp_ue=0; + fp_ze=0; + fp_xe=0; +} + +# mffscrn 111111 ..... 10110 ..... 10010 00111/ +:mffscrn fT, fB is $(NOTVLE) & OP=63 & fT & BITS_16_20=22 & fB & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_rn0=fB[1,1]; + fp_rn1=fB[0,1]; +} + +# mffscrni 111111 ..... 10111 ///.. 10010 00111/ +:mffscrni fT, RM is $(NOTVLE) & OP=63 & fT & BITS_16_20=23 & BITS_13_15=0 & RM & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + _tmpRM:1 = RM; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; + fp_rn0=_tmpRM[0,1]; + fp_rn1=_tmpRM[1,1]; +} + + +:mffsl fT is $(NOTVLE) & OP=63 & fT & BITS_11_20=24 & XOP_1_10=583 & BIT_0=0 { + tmp:8 = 0; + packFPSCR(tmp); + fT = tmp & 0x7000000ff; +} +@endif + +# msgclru 011111 ///// ///// ..... 00011 01110/ +# Message Clear Ultravisor +:msgclru B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=10 & BIT_0=0 { + MessageClear(B); +} + +# msgsndu 011111 ///// ///// ..... 00010 01110/ +# Message Send Ultravisor +:msgsndu B is $(NOTVLE) & OP=31 & BITS_21_25=0 & BITS_16_20=0 & B & XOP_1_10=78 & BIT_0=0 { + MessageSend(B); +} + +# urfid 000100 ..... ..... ..... ..... 100011 +# Ultravisor Return from Interrupt Doubleword +:rfid is $(NOTVLE) & OP=19 & BITS_11_25=0 & XOP_1_10=306 & BIT_0=0 +{ + MSR = returnFromInterrupt(MSR, SRR1); + local ra = SRR0; + return[ra]; +} + +# slbiag 011111 ..... ///// ..... 11010 10010/ +# SLB Invalidate All Global +define pcodeop SLBInvalidateAllGlobal; +:slbiag S, LBIT is $(NOTVLE) & OP=31 & S & BITS_17_20=0 & LBIT & BITS_11_15=0 & XOP_1_10=850 & BIT_0=0 { + SLBInvalidateAllGlobal(S, LBIT:1); +} + + diff --git a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc index 1b0e76cda8..a0dac54792 100644 --- a/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc +++ b/Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc @@ -749,7 +749,7 @@ N_0txx: r0",@"^N_0 is r0 & N_0 { tmp:4 = N_0; export tmp; } # text bsr # arch arch_sh_up :bsr I_1tbranch is OP_0=0xb & I_1tbranch { - + PR = inst_next; delayslot(1); call I_1tbranch; }