From c9be1860c181581ee192cb86e97eeec983a6bf00 Mon Sep 17 00:00:00 2001 From: Sleigh-InSPECtor Date: Tue, 28 May 2024 17:09:24 +0930 Subject: [PATCH] AArch32: fixed ldrexd * fixed addr src register aliased as first dest register of a double word load causing second word load at the value of first load --- Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc index 4eba7c1b6b..0fc0d9b69a 100644 --- a/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc +++ b/Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc @@ -2868,9 +2868,10 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate :ldrexd^COND Rd,Rd2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1b & Rn & Rd & Rd2 & c0011=0xf9f { - build COND; - Rd = *(Rn); - Rd2 = *(Rn + 4); + build COND; + local addr:4 = Rn; + Rd = *(addr); + Rd2 = *(addr + 4); } :ldrexh^COND Rd,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1f & Rn & Rd & c0011=0xf9f