From 8a09a052583f60432b68bcadcdc5adfb5fbf16e5 Mon Sep 17 00:00:00 2001
From: ghidorahrex <ghidorahrex@users.noreply.github.com>
Date: Thu, 7 May 2026 16:37:12 +0000
Subject: [PATCH] GP-6798: Corrected CIP-51 language definition

---
 Ghidra/Processors/8051/certification.manifest |   1 +
 .../Processors/8051/data/languages/8051.ldefs |  12 +
 .../8051/data/languages/cip-51.pspec          | 389 ++++++++++++++++++
 .../8051/data/languages/keil-cx51.cspec       | 187 ++++-----
 4 files changed, 475 insertions(+), 114 deletions(-)
 create mode 100644 Ghidra/Processors/8051/data/languages/cip-51.pspec

diff --git a/Ghidra/Processors/8051/certification.manifest b/Ghidra/Processors/8051/certification.manifest
index 5dac87b24b..62a314ac8d 100644
--- a/Ghidra/Processors/8051/certification.manifest
+++ b/Ghidra/Processors/8051/certification.manifest
@@ -14,6 +14,7 @@ data/languages/8051.pspec||GHIDRA||||END|
 data/languages/8051.slaspec||GHIDRA||||END|
 data/languages/8051_archimedes.cspec||GHIDRA||||END|
 data/languages/8051_main.sinc||GHIDRA||||END|
+data/languages/cip-51.pspec||GHIDRA||||END|
 data/languages/cip-51.slaspec||GHIDRA||||END|
 data/languages/keil-cx51.cspec||GHIDRA||||END|
 data/languages/mx51.cspec||GHIDRA||||END|
diff --git a/Ghidra/Processors/8051/data/languages/8051.ldefs b/Ghidra/Processors/8051/data/languages/8051.ldefs
index 7c2700ffe8..ef4f11cc4f 100644
--- a/Ghidra/Processors/8051/data/languages/8051.ldefs
+++ b/Ghidra/Processors/8051/data/languages/8051.ldefs
@@ -50,4 +50,16 @@
     <compiler name="default" spec="mx51.cspec" id="default"/>
     <external_name tool="IDA-PRO" name="8051"/>
   </language>
+  <language processor="8051"
+            endian="big"
+            size="24"
+            variant="cip-51"
+            version="1.0"
+            slafile="cip-51.sla"
+            processorspec="cip-51.pspec"
+            manualindexfile="../manuals/8051.idx"
+            id="8051:BE:24:cip-51">
+    <description>Silicon Labs CIP-51 Microcontroller Family</description>
+    <compiler name="default" spec="keil-cx51.cspec" id="default"/>
+  </language>
 </language_definitions>
diff --git a/Ghidra/Processors/8051/data/languages/cip-51.pspec b/Ghidra/Processors/8051/data/languages/cip-51.pspec
new file mode 100644
index 0000000000..d342b93819
--- /dev/null
+++ b/Ghidra/Processors/8051/data/languages/cip-51.pspec
@@ -0,0 +1,389 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+
+  <programcounter register="PC"/>
+  
+  <volatile outputop="write_volatile" inputop="read_volatile">
+    <range space="SFR" first="0x0" last="0xFF"/>
+    <range space="BITS" first="0x80" last="0xFF"/>
+  </volatile>
+  
+  <default_symbols>
+
+    <symbol name="BANK0_R0" address="INTMEM:00"/>
+    <symbol name="BANK0_R1" address="INTMEM:01"/>
+    <symbol name="BANK0_R2" address="INTMEM:02"/>
+    <symbol name="BANK0_R3" address="INTMEM:03"/>
+    <symbol name="BANK0_R4" address="INTMEM:04"/>
+    <symbol name="BANK0_R5" address="INTMEM:05"/>
+    <symbol name="BANK0_R6" address="INTMEM:06"/>
+    <symbol name="BANK0_R7" address="INTMEM:07"/>
+    
+    <symbol name="BANK1_R0" address="INTMEM:08"/>
+    <symbol name="BANK1_R1" address="INTMEM:09"/>
+    <symbol name="BANK1_R2" address="INTMEM:0a"/>
+    <symbol name="BANK1_R3" address="INTMEM:0b"/>
+    <symbol name="BANK1_R4" address="INTMEM:0c"/>
+    <symbol name="BANK1_R5" address="INTMEM:0d"/>
+    <symbol name="BANK1_R6" address="INTMEM:0e"/>
+    <symbol name="BANK1_R7" address="INTMEM:0f"/>
+    
+    <symbol name="BANK2_R0" address="INTMEM:10"/>
+    <symbol name="BANK2_R1" address="INTMEM:11"/>
+    <symbol name="BANK2_R2" address="INTMEM:12"/>
+    <symbol name="BANK2_R3" address="INTMEM:13"/>
+    <symbol name="BANK2_R4" address="INTMEM:14"/>
+    <symbol name="BANK2_R5" address="INTMEM:15"/>
+    <symbol name="BANK2_R6" address="INTMEM:16"/>
+    <symbol name="BANK2_R7" address="INTMEM:17"/>
+    
+    <symbol name="BANK3_R0" address="INTMEM:18"/>
+    <symbol name="BANK3_R1" address="INTMEM:19"/>
+    <symbol name="BANK3_R2" address="INTMEM:1a"/>
+    <symbol name="BANK3_R3" address="INTMEM:1b"/>
+    <symbol name="BANK3_R4" address="INTMEM:1c"/>
+    <symbol name="BANK3_R5" address="INTMEM:1d"/>
+    <symbol name="BANK3_R6" address="INTMEM:1e"/>
+    <symbol name="BANK3_R7" address="INTMEM:1f"/>
+  
+    <symbol name="P0"       address="SFR:80"/>  <!-- Pages: All -->
+    <symbol name="SP"       address="SFR:81"/>  <!-- Pages: All -->
+    <symbol name="DPL"      address="SFR:82"/>  <!-- Pages: All -->
+    <symbol name="DPH"      address="SFR:83"/>  <!-- Pages: All -->
+    <symbol name="SFRPAGE"  address="SFR:84"/>  <!-- Pages: All -->
+    <symbol name="SFRNEXT"  address="SFR:85"/>  <!-- Pages: All -->
+    <symbol name="SFRLAST"  address="SFR:86"/>  <!-- Pages: All -->
+    <symbol name="PCON"     address="SFR:87"/>  <!-- Pages: All -->
+    <symbol name="TCON"     address="SFR:88"/>
+    <symbol name="TMOD"     address="SFR:89"/>
+    <symbol name="TL0"      address="SFR:8a"/>
+    <symbol name="TL1"      address="SFR:8b"/>
+    <symbol name="TH0"      address="SFR:8c"/>
+    <symbol name="TH1"      address="SFR:8d"/>
+    <symbol name="FADDR"    address="SFR:8f"/>
+    <symbol name="P1"       address="SFR:90"/>  <!-- Pages: All -->
+    <symbol name="SCON0"    address="SFR:98"/>  <!-- Pages: 0 -->
+    <symbol name="SBUF0"    address="SFR:99"/>  <!-- Pages: 0 -->
+    <symbol name="P2"       address="SFR:a0"/>  <!-- Pages: All -->
+    <symbol name="IE"       address="SFR:a8"/>  <!-- Pages: All -->
+    <symbol name="SADDR0"   address="SFR:a9"/>  <!-- Pages:0 -->
+    <symbol name="P3"       address="SFR:b0"/>  <!-- Pages: All -->
+    <symbol name="PSBANK"   address="SFR:b1"/>  <!-- Pages: All -->
+    <symbol name="FLSCL"    address="SFR:b7"/>  <!-- Pages: 0 -->
+    <symbol name="SADEN0"   address="SFR:b9"/>  <!-- Pages: 0 -->
+    <symbol name="TMR2CN"   address="SFR:c8"/>  <!-- Pages: 0 -->
+    <symbol name="TMR2CF"   address="SFR:c9"/>  <!-- Pages: 0 -->
+    <symbol name="RCAP2L"   address="SFR:ca"/>  <!-- Pages: 0 -->
+    <symbol name="RCAP2H"   address="SFR:cb"/>  <!-- Pages: 0 -->
+    <symbol name="TMR2L"    address="SFR:cc"/>  <!-- Pages: 0 -->
+    <symbol name="TMR2H"    address="SFR:cd"/>  <!-- Pages: 0 -->
+    <symbol name="PSW"      address="SFR:d0"/>  <!-- Pages: All -->
+    <symbol name="REF0CN"   address="SFR:d1"/>  <!-- Pages: 0 -->
+    <symbol name="DAC0L"    address="SFR:d2"/>  <!-- Pages: 0 -->
+    <symbol name="DAC0H"    address="SFR:d3"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CN"   address="SFR:d8"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0MD"   address="SFR:d9"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM0" address="SFR:da"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM1" address="SFR:db"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM2" address="SFR:dc"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM3" address="SFR:dd"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM4" address="SFR:de"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPM5" address="SFR:df"/>  <!-- Pages: 0 -->
+    <symbol name="ACC"      address="SFR:e0"/>  <!-- Pages: All -->
+    <symbol name="PCA0CL5"  address="SFR:e1"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CH5"  address="SFR:e2"/>  <!-- Pages: 0 -->
+    <symbol name="EIE1"     address="SFR:e6"/>  <!-- Pages: All -->
+    <symbol name="EIE2"     address="SFR:e7"/>  <!-- Pages: All -->
+    <symbol name="EIP1"     address="SFR:e8"/>  <!-- Pages: All -->
+    <symbol name="EIP2"     address="SFR:e9"/>  <!-- Pages: All -->
+    <symbol name="PCA0CPH2" address="SFR:ea"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPL2" address="SFR:eb"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPH3" address="SFR:ec"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPL4" address="SFR:ed"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPH4" address="SFR:ee"/>  <!-- Pages: 0 -->
+    <symbol name="B"        address="SFR:f0"/>  <!-- Pages: All -->
+    <symbol name="EIP1"     address="SFR:f6"/>  <!-- Pages: All -->
+    <symbol name="EIP2"     address="SFR:f7"/>  <!-- Pages: All -->
+    <symbol name="PCA00L"   address="SFR:f9"/>  <!-- Pages: 0 -->
+    <symbol name="PCA00H"   address="SFR:fa"/>  <!-- Pages: 0 -->
+    <symbol name="PCA0CPL0" address="SFR:fb"/>
+    <symbol name="PCA0CPH0" address="SFR:fc"/>
+    <symbol name="PCA0CPL1" address="SFR:fd"/>
+    <symbol name="PCA0CPH"  address="SFR:fe"/>
+    
+    <symbol name="20.0" address="BITS:00"/>
+    <symbol name="20.1" address="BITS:01"/>
+    <symbol name="20.2" address="BITS:02"/>
+    <symbol name="20.3" address="BITS:03"/>
+    <symbol name="20.4" address="BITS:04"/>
+    <symbol name="20.5" address="BITS:05"/>
+    <symbol name="20.6" address="BITS:06"/>
+    <symbol name="20.7" address="BITS:07"/>
+    <symbol name="21.0" address="BITS:08"/>
+    <symbol name="21.1" address="BITS:09"/>
+    <symbol name="21.2" address="BITS:0a"/>
+    <symbol name="21.3" address="BITS:0b"/>
+    <symbol name="21.4" address="BITS:0c"/>
+    <symbol name="21.5" address="BITS:0d"/>
+    <symbol name="21.6" address="BITS:0e"/>
+    <symbol name="21.7" address="BITS:0f"/>
+    <symbol name="22.0" address="BITS:10"/>
+    <symbol name="22.1" address="BITS:11"/>
+    <symbol name="22.2" address="BITS:12"/>
+    <symbol name="22.3" address="BITS:13"/>
+    <symbol name="22.4" address="BITS:14"/>
+    <symbol name="22.5" address="BITS:15"/>
+    <symbol name="22.6" address="BITS:16"/>
+    <symbol name="22.7" address="BITS:17"/>
+    <symbol name="23.0" address="BITS:18"/>
+    <symbol name="23.1" address="BITS:19"/>
+    <symbol name="23.2" address="BITS:1a"/>
+    <symbol name="23.3" address="BITS:1b"/>
+    <symbol name="23.4" address="BITS:1c"/>
+    <symbol name="23.5" address="BITS:1d"/>
+    <symbol name="23.6" address="BITS:1e"/>
+    <symbol name="23.7" address="BITS:1f"/>
+    <symbol name="24.0" address="BITS:20"/>
+    <symbol name="24.1" address="BITS:21"/>
+    <symbol name="24.2" address="BITS:22"/>
+    <symbol name="24.3" address="BITS:23"/>
+    <symbol name="24.4" address="BITS:24"/>
+    <symbol name="24.5" address="BITS:25"/>
+    <symbol name="24.6" address="BITS:26"/>
+    <symbol name="24.7" address="BITS:27"/>
+    <symbol name="25.0" address="BITS:28"/>
+    <symbol name="25.1" address="BITS:29"/>
+    <symbol name="25.2" address="BITS:2a"/>
+    <symbol name="25.3" address="BITS:2b"/>
+    <symbol name="25.4" address="BITS:2c"/>
+    <symbol name="25.5" address="BITS:2d"/>
+    <symbol name="25.6" address="BITS:2e"/>
+    <symbol name="25.7" address="BITS:2f"/>
+    <symbol name="26.0" address="BITS:30"/>
+    <symbol name="26.1" address="BITS:31"/>
+    <symbol name="26.2" address="BITS:32"/>
+    <symbol name="26.3" address="BITS:33"/>
+    <symbol name="26.4" address="BITS:34"/>
+    <symbol name="26.5" address="BITS:35"/>
+    <symbol name="26.6" address="BITS:36"/>
+    <symbol name="26.7" address="BITS:37"/>
+    <symbol name="27.0" address="BITS:38"/>
+    <symbol name="27.1" address="BITS:39"/>
+    <symbol name="27.2" address="BITS:3a"/>
+    <symbol name="27.3" address="BITS:3b"/>
+    <symbol name="27.4" address="BITS:3c"/>
+    <symbol name="27.5" address="BITS:3d"/>
+    <symbol name="27.6" address="BITS:3e"/>
+    <symbol name="27.7" address="BITS:3f"/>
+    <symbol name="28.0" address="BITS:40"/>
+    <symbol name="28.1" address="BITS:41"/>
+    <symbol name="28.2" address="BITS:42"/>
+    <symbol name="28.3" address="BITS:43"/>
+    <symbol name="28.4" address="BITS:44"/>
+    <symbol name="28.5" address="BITS:45"/>
+    <symbol name="28.6" address="BITS:46"/>
+    <symbol name="28.7" address="BITS:47"/>
+    <symbol name="29.0" address="BITS:48"/>
+    <symbol name="29.1" address="BITS:49"/>
+    <symbol name="29.2" address="BITS:4a"/>
+    <symbol name="29.3" address="BITS:4b"/>
+    <symbol name="29.4" address="BITS:4c"/>
+    <symbol name="29.5" address="BITS:4d"/>
+    <symbol name="29.6" address="BITS:4e"/>
+    <symbol name="29.7" address="BITS:4f"/>
+    <symbol name="2a.0" address="BITS:50"/>
+    <symbol name="2a.1" address="BITS:51"/>
+    <symbol name="2a.2" address="BITS:52"/>
+    <symbol name="2a.3" address="BITS:53"/>
+    <symbol name="2a.4" address="BITS:54"/>
+    <symbol name="2a.5" address="BITS:55"/>
+    <symbol name="2a.6" address="BITS:56"/>
+    <symbol name="2a.7" address="BITS:57"/>
+    <symbol name="2b.0" address="BITS:58"/>
+    <symbol name="2b.1" address="BITS:59"/>
+    <symbol name="2b.2" address="BITS:5a"/>
+    <symbol name="2b.3" address="BITS:5b"/>
+    <symbol name="2b.4" address="BITS:5c"/>
+    <symbol name="2b.5" address="BITS:5d"/>
+    <symbol name="2b.6" address="BITS:5e"/>
+    <symbol name="2b.7" address="BITS:5f"/>
+    <symbol name="2c.0" address="BITS:60"/>
+    <symbol name="2c.1" address="BITS:61"/>
+    <symbol name="2c.2" address="BITS:62"/>
+    <symbol name="2c.3" address="BITS:63"/>
+    <symbol name="2c.4" address="BITS:64"/>
+    <symbol name="2c.5" address="BITS:65"/>
+    <symbol name="2c.6" address="BITS:66"/>
+    <symbol name="2c.7" address="BITS:67"/>
+    <symbol name="2d.0" address="BITS:68"/>
+    <symbol name="2d.1" address="BITS:69"/>
+    <symbol name="2d.2" address="BITS:6a"/>
+    <symbol name="2d.3" address="BITS:6b"/>
+    <symbol name="2d.4" address="BITS:6c"/>
+    <symbol name="2d.5" address="BITS:6d"/>
+    <symbol name="2d.6" address="BITS:6e"/>
+    <symbol name="2d.7" address="BITS:6f"/>
+    <symbol name="2e.0" address="BITS:70"/>
+    <symbol name="2e.1" address="BITS:71"/>
+    <symbol name="2e.2" address="BITS:72"/>
+    <symbol name="2e.3" address="BITS:73"/>
+    <symbol name="2e.4" address="BITS:74"/>
+    <symbol name="2e.5" address="BITS:75"/>
+    <symbol name="2e.6" address="BITS:76"/>
+    <symbol name="2e.7" address="BITS:77"/>
+    <symbol name="2f.0" address="BITS:78"/>
+    <symbol name="2f.1" address="BITS:79"/>
+    <symbol name="2f.2" address="BITS:7a"/>
+    <symbol name="2f.3" address="BITS:7b"/>
+    <symbol name="2f.4" address="BITS:7c"/>
+    <symbol name="2f.5" address="BITS:7d"/>
+    <symbol name="2f.6" address="BITS:7e"/>
+    <symbol name="2f.7" address="BITS:7f"/>
+    
+    <symbol name="P0.0" address="BITS:80"/>
+    <symbol name="P0.1" address="BITS:81"/>
+    <symbol name="P0.2" address="BITS:82"/>
+    <symbol name="P0.3" address="BITS:83"/>
+    <symbol name="P0.4" address="BITS:84"/>
+    <symbol name="P0.5" address="BITS:85"/>
+    <symbol name="P0.6" address="BITS:86"/>
+    <symbol name="P0.7" address="BITS:87"/>
+    <symbol name="IT0" address="BITS:88"/>
+    <symbol name="IE0" address="BITS:89"/>
+    <symbol name="IT1" address="BITS:8a"/>
+    <symbol name="IE1" address="BITS:8b"/>
+    <symbol name="TR0" address="BITS:8c"/>
+    <symbol name="TF0" address="BITS:8d"/>
+    <symbol name="TR1" address="BITS:8e"/>
+    <symbol name="TF1" address="BITS:8f"/>
+    <symbol name="P1.0" address="BITS:90"/>
+    <symbol name="P1.1" address="BITS:91"/>
+    <symbol name="P1.2" address="BITS:92"/>
+    <symbol name="P1.3" address="BITS:93"/>
+    <symbol name="P1.4" address="BITS:94"/>
+    <symbol name="P1.5" address="BITS:95"/>
+    <symbol name="P1.6" address="BITS:96"/>
+    <symbol name="P1.7" address="BITS:97"/>
+    <symbol name="RI" address="BITS:98"/>
+    <symbol name="TI" address="BITS:99"/>
+    <symbol name="RB8" address="BITS:9a"/>
+    <symbol name="TB8" address="BITS:9b"/>
+    <symbol name="REN" address="BITS:9c"/>
+    <symbol name="SM2" address="BITS:9d"/>
+    <symbol name="SM1" address="BITS:9e"/>
+    <symbol name="SM0" address="BITS:9f"/>
+    <symbol name="P2.0" address="BITS:a0"/>
+    <symbol name="P2.1" address="BITS:a1"/>
+    <symbol name="P2.2" address="BITS:a2"/>
+    <symbol name="P2.3" address="BITS:a3"/>
+    <symbol name="P2.4" address="BITS:a4"/>
+    <symbol name="P2.5" address="BITS:a5"/>
+    <symbol name="P2.6" address="BITS:a6"/>
+    <symbol name="P2.7" address="BITS:a7"/>
+    <symbol name="EX0" address="BITS:a8"/>
+    <symbol name="ET0" address="BITS:a9"/>
+    <symbol name="EX1" address="BITS:aa"/>
+    <symbol name="ET1" address="BITS:ab"/>
+    <symbol name="ES" address="BITS:ac"/>
+    <symbol name="ET2" address="BITS:ad"/>
+    <symbol name="EC" address="BITS:ae"/>
+    <symbol name="EA" address="BITS:af"/>
+    <symbol name="RXD" address="BITS:b0"/>
+    <symbol name="TXD" address="BITS:b1"/>
+    <symbol name="INT0" address="BITS:b2"/>
+    <symbol name="INT1" address="BITS:b3"/>
+    <symbol name="T0" address="BITS:b4"/>
+    <symbol name="T1" address="BITS:b5"/>
+    <symbol name="WR" address="BITS:b6"/>
+    <symbol name="RD" address="BITS:b7"/>
+    <symbol name="PX0" address="BITS:b8"/>
+    <symbol name="PT0" address="BITS:b9"/>
+    <symbol name="PX1" address="BITS:ba"/>
+    <symbol name="PT1" address="BITS:bb"/>
+    <symbol name="PS" address="BITS:bc"/>
+    <symbol name="PT2" address="BITS:bd"/>
+    <symbol name="PC" address="BITS:be"/>
+    <symbol name="IP.7" address="BITS:bf"/>
+    <symbol name="FIFLG.0" address="BITS:c0"/>
+    <symbol name="FIFLG.1" address="BITS:c1"/>
+    <symbol name="FIFLG.2" address="BITS:c2"/>
+    <symbol name="FIFLG.3" address="BITS:c3"/>
+    <symbol name="FIFLG.4" address="BITS:c4"/>
+    <symbol name="FIFLG.5" address="BITS:c5"/>
+    <symbol name="FIFLG.6" address="BITS:c6"/>
+    <symbol name="FIFLG.7" address="BITS:c7"/>
+    <symbol name="CPRL2" address="BITS:c8"/>
+    <symbol name="CT2" address="BITS:c9"/>
+    <symbol name="TR2" address="BITS:ca"/>
+    <symbol name="EXEN2" address="BITS:cb"/>
+    <symbol name="TCLK" address="BITS:cc"/>
+    <symbol name="RCLK" address="BITS:cd"/>
+    <symbol name="EXF2" address="BITS:ce"/>
+    <symbol name="TF2" address="BITS:cf"/>
+    <symbol name="P" address="BITS:d0"/>
+    <symbol name="UD" address="BITS:d1"/>
+    <symbol name="OV" address="BITS:d2"/>
+    <symbol name="RS0" address="BITS:d3"/>
+    <symbol name="RS1" address="BITS:d4"/>
+    <symbol name="F0" address="BITS:d5"/>
+    <symbol name="AC" address="BITS:d6"/>
+    <symbol name="C" address="BITS:d7"/>
+    <symbol name="CCF.0" address="BITS:d8"/>
+    <symbol name="CCF.1" address="BITS:d9"/>
+    <symbol name="CCF.2" address="BITS:da"/>
+    <symbol name="CCF.3" address="BITS:db"/>
+    <symbol name="CCF.4" address="BITS:dc"/>
+    <symbol name="CCON.5" address="BITS:dd"/>
+    <symbol name="CR" address="BITS:de"/>
+    <symbol name="CF" address="BITS:df"/>
+    <symbol name="ACC.0" address="BITS:e0"/>
+    <symbol name="ACC.1" address="BITS:e1"/>
+    <symbol name="ACC.2" address="BITS:e2"/>
+    <symbol name="ACC.3" address="BITS:e3"/>
+    <symbol name="ACC.4" address="BITS:e4"/>
+    <symbol name="ACC.5" address="BITS:e5"/>
+    <symbol name="ACC.6" address="BITS:e6"/>
+    <symbol name="ACC.7" address="BITS:e7"/>
+    <symbol name="HIFLG.0" address="BITS:e8"/>
+    <symbol name="HIFLG.1" address="BITS:e9"/>
+    <symbol name="HIFLG.2" address="BITS:ea"/>
+    <symbol name="HIFLG.3" address="BITS:eb"/>
+    <symbol name="HIFLG.4" address="BITS:ec"/>
+    <symbol name="HIFLG.5" address="BITS:ed"/>
+    <symbol name="HIFLG.6" address="BITS:ee"/>
+    <symbol name="HIFLG.7" address="BITS:ef"/>
+    <symbol name="B.0" address="BITS:f0"/>
+    <symbol name="B.1" address="BITS:f1"/>
+    <symbol name="B.2" address="BITS:f2"/>
+    <symbol name="B.3" address="BITS:f3"/>
+    <symbol name="B.4" address="BITS:f4"/>
+    <symbol name="B.5" address="BITS:f5"/>
+    <symbol name="B.6" address="BITS:f6"/>
+    <symbol name="B.7" address="BITS:f7"/>
+    <symbol name="F8.0" address="BITS:f8"/>
+    <symbol name="F8.1" address="BITS:f9"/>
+    <symbol name="F8.2" address="BITS:fa"/>
+    <symbol name="F8.3" address="BITS:fb"/>
+    <symbol name="F8.4" address="BITS:fc"/>
+    <symbol name="F8.5" address="BITS:fd"/>
+    <symbol name="F8.6" address="BITS:fe"/>
+    <symbol name="F8.7" address="BITS:ff"/>
+
+  </default_symbols>
+  
+  <default_memory_blocks>
+    <memory_block name="REG_BANK_1" start_address="INTMEM:0" length="0x8" initialized="false"/>
+    <memory_block name="REG_BANK_2" start_address="INTMEM:8" length="0x8" initialized="false"/>
+    <memory_block name="REG_BANK_3" start_address="INTMEM:10" length="0x8" initialized="false"/>
+    <memory_block name="REG_BANK_4" start_address="INTMEM:18" length="0x8" initialized="false"/>
+    <memory_block name="INTMEM" start_address="INTMEM:20" length="0xe0" initialized="false"/>
+    <memory_block name="BITS" start_address="BITS:00" bit_mapped_address="INTMEM:20" length="0x80"/>
+    <memory_block name="SFR" start_address="SFR:80" length="0x80" initialized="false"/>
+    
+    <!--  BUG: SFR-BITS do not map properly since only every 8th SFR register is mapped (e.g., 0x80, 0x88, 0x90 ... 0xF0, 0xF8) -->
+    <memory_block name="SFR-BITS" start_address="BITS:80" bit_mapped_address="SFR:80" length="0x80"/>
+    
+  </default_memory_blocks>
+  
+</processor_spec>
diff --git a/Ghidra/Processors/8051/data/languages/keil-cx51.cspec b/Ghidra/Processors/8051/data/languages/keil-cx51.cspec
index 14efe89087..b74d95487c 100644
--- a/Ghidra/Processors/8051/data/languages/keil-cx51.cspec
+++ b/Ghidra/Processors/8051/data/languages/keil-cx51.cspec
@@ -1,118 +1,77 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <compiler_spec>
-<!-- Since data_organization isn't present in the other 8051-family cspecs, I suspect
-   - it's not needed here either, so although I've provided what I hope would be appropriate
-   - if it should prove necessary, I've commented it out.
-  -->
-<!--
- <data_organization>
-   <absolute_max_alignment value="0" />
-   <machine_alignment value="1" />
-   <default_alignment value="1" />
-   <default_pointer_alignment value="1" />
-   <pointer_size value="2" />
-   <wchar_size value="1" />
-   <short_size value="2" />
-   <integer_size value="2" />
-   <long_size value="4" />
-   <long_long_size value="4" />
-   <float_size value="4" />
-   <double_size value="4" />
-   <long_double_size value="4" />
-   <size_alignment_map>
-     <entry size="1" alignment="1" />
-     <entry size="2" alignment="1" />
-     <entry size="4" alignment="1" />
-   </size_alignment_map>
- </data_organization>
--->
+  <global>
+    <range space="IFLASH"/>
+    <range space="CODE"/>
+    <range space="INTMEM"/>
+    <range space="SFR"/>
+    <range space="XRAM"/>
+    <range space="RAM"/>
+    <range space="BITS"/>
+  </global>
+  <stackpointer register="SP" space="RAM" growth="positive"/>
+  <default_proto>
+    <prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
+      <input>
+        <pentry minsize="1" maxsize="1" metatype="float">
+          <register name="R4"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1" metatype="float">
+          <register name="R5"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R7"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R6"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R5"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R4"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R3"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4">
+          <addr space="RAM" offset="0"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="1">
+          <register name="R7"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R6"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R7"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R4"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R5"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R6"/>
+        </pentry>
+        <pentry minsize="1" maxsize="1">
+          <register name="R7"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="SP"/>
+        <register name="PSW"/>
+      </unaffected>
+    </prototype>
+  </default_proto>
 
- <global>
-   <range space="IFLASH"/>
-   <range space="CODE"/>
-   <range space="INTMEM"/>
-   <range space="SFR"/>
-   <range space="XRAM"/>
-   <range space="RAM"/>
-   <range space="BITS"/>
- </global>
+  <funcptr align="2" />
+  <aggressivetrim signext="true"/>
+  <returnaddress>
+    <varnode space="stack" offset="0" size="2"/>
+  </returnaddress>
 
- <stackpointer register="SP" space="RAM" growth="positive"/>
-
- <default_proto>
-   <prototype name="__stdcall" extrapop="2" stackshift="2" strategy="register">
-     <input>
-       <pentry minsize="1" maxsize="1" metatype="float">
-         <register name="R4"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1" metatype="float">
-         <register name="R5"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R7"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R6"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R5"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R4"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R3"/>
-       </pentry>
-       <pentry minsize="1" maxsize="4">
-         <addr space="RAM" offset="0"/>
-       </pentry>
-     </input>
-     <output>
-       <pentry minsize="1" maxsize="1">
-         <register name="R7"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R6"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R7"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R4"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R5"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R6"/>
-       </pentry>
-       <pentry minsize="1" maxsize="1">
-         <register name="R7"/>
-       </pentry>
-     </output>
-     <unaffected>
-       <register name="SP"/>
-       <register name="PSW"/>
-     </unaffected>
-   </prototype>
- </default_proto>
-
- <funcptr align="2" />
- <aggressivetrim signext="true"/>
- <returnaddress>
-   <varnode space="stack" offset="0" size="2"/>
- </returnaddress>
-
- <segmentop space="CODE" userop="segment" farpointer="yes">
-   <pcode>
-     <input name="baseValue" size="2"/>
-     <input name="innerValue" size="2"/>
-     <output name="res" size="4"/>
-     <body><![CDATA[
-       res = baseValue;
-       res = res << 16;
-       res = res | innerValue;
-     ]]></body>
-   </pcode>
- </segmentop>
-</compiler_spec>
\ No newline at end of file
+</compiler_spec>