From f18269b0eb079165df3627063f6c2e1d6bbbb3b2 Mon Sep 17 00:00:00 2001
From: p-mikeg <mike.greenbaum@mail.huji.ac.il>
Date: Tue, 14 Jul 2026 00:53:15 +0300
Subject: [PATCH] Fix sev.w arm encoding.

Unlike the other hints, sev.w op0 missed the 0x in the beginning which led to incorrect parsing.
The encoding should be 0xf3af8004 (https://developer.arm.com/documentation/ddi0403/latest/,
sev encoding T2).
---
 Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
index a56103c476..26a34b4630 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
@@ -4358,7 +4358,7 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; }
    build ItCond;
 }
 
-:sev^ItCond^".w"                      is TMode=1 & ItCond & op0=0xf3af; op0=8004
+:sev^ItCond^".w"                      is TMode=1 & ItCond & op0=0xf3af; op0=0x8004
 {
    build ItCond;
 }