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arch: riscv: Add RISCV_ISA_EXTRA config string

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Adds a new user-configurable string to arch/Config.in.riscv, and in
arch/arch.mk.riscv appends it to GCC_TARGET_ARCH.

This enables custom extensions/combinations to be easily configured.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Arnout:
 - fix check-package warnings
 - introduce ARCH_RISV_ISA_EXTRA to simplify stripping of quotes
]
Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
This commit is contained in:
Charlie Jenkins
2025-05-07 15:50:53 -07:00
committed by Arnout Vandecappelle
parent ed9466e7f9
commit 166bfd3e66
2 changed files with 12 additions and 0 deletions
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7
arch/Config.in.riscv
View File

@@ -45,6 +45,13 @@ config BR2_RISCV_ISA_RVV
bool "Vector Instructions (V)" bool "Vector Instructions (V)"
select BR2_ARCH_NEEDS_GCC_AT_LEAST_12 select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
config BR2_RISCV_ISA_EXTRA
string "Append extra RISC-V ISA extensions"
help
Extra ISA extensions to append to the ISA extensions string.
They are underscore-separated. For example,
"zba_zbb_zvl256b".
choice choice
prompt "Target Architecture Size" prompt "Target Architecture Size"
default BR2_RISCV_64 default BR2_RISCV_64

5
arch/arch.mk.riscv
View File

@@ -39,4 +39,9 @@ ifeq ($(BR2_TOOLCHAIN_GCC_AT_LEAST_12),y)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_zicsr_zifencei
endif endif
ARCH_RISV_ISA_EXTRA = $(call qstrip, $(BR2_RISCV_ISA_EXTRA))
ifneq ($(ARCH_RISV_ISA_EXTRA),)
GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)_$(ARCH_RISV_ISA_EXTRA)
endif
endif endif