383 Commits

Author SHA1 Message Date
Peter Korsgaard
c7f2991ac3 Merge branch 'next'
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2026-06-09 14:55:26 +02:00
Julien Olivain
da1b45dd00 arch/Config.in.powerpc: add Power11 CPU type
This commit adds the IBM Power11 CPU type.

This CPU is supported in gcc since v15.1.0 (see upstream commit [1]),
and in binutils since v2.35 (the gas -mpower11 option is documented
since upstream commit [2]).

[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=05f0e9eec9f9beeffe024ecd6566b41200d79cff
[2] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4199cf1e152daab0460f08cc7dbd1f727ac3e4cc

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2026-05-30 16:52:06 +02:00
Julien Olivain
3523e1ac79 arch/Config.in.powerpc: add Power10 CPU type
This commit adds the IBM Power10 CPU type. See [1].

This CPU is supported in gcc since v11.1.0 (see upstream commit [2]),
and in binutils since v2.35 (the gas -mpower10 option is documented
since upstream commit [3]).

[1] https://en.wikipedia.org/wiki/Power10
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5d9d0c94588c8834a33eca6847b0a1401353300b
[3] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=1424c35d071e7d49a4a219c7dee8c88ffd60ddca

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2026-05-30 16:51:23 +02:00
Bernd Kuhls
504840bcc2 arch/Config.in: introduce BR2_ARCH_NEEDS_GCC_AT_LEAST_17
Signed-off-by: Bernd Kuhls <bernd@kuhls.net>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-05-30 15:48:42 +02:00
Vincent Stehlé
b854bce8b0 arch/hppa: remove pa-risc 1.0
The new glibc 2.43 we have in Buildroot since commit [1] introduced changes
around 64B atomics [2], which break the build for PA-RISC 1.0. [3]

This is the only C library we support at this point; forcing soft-float
seems to be a workaround, but as this architecture version was not as
widely used as the later 1.1 and we have no hardware or simulator for it at
this point, remove it completely instead to spare the autobuilders.

Link: 227378b593 [1]
Link: https://sourceware.org/git/?p=glibc.git;a=commit;h=9da0585852e5599ad6e849ccdf2f6f9b04038a3c [2]
Link: https://autobuild.buildroot.org/results/905c7e8db0f8b9014f26925c6e1379a0c54ad446/ [3]
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
2026-05-30 15:09:44 +02:00
Daniel Palmer
e5c7b43494 arch/m68k: add 68000 nommu support
Everyone thinks they like ARM but secretly they want to run
Linux on their Megadrive[0].

Building a working toolchain/userland for nommu m68k is a bit
difficult because of the bitrotten tools all over the place and
one big issue is GCC generates code that uses unaligned
accesses that will cause an exception on 68000 machines if you
aren't careful.

Buildroot can easily create a working toolchain and userland
for nommu m68k so why not?

0 - This isn't a joke, I'm working on this. I have u-boot working
    on the Megadrive, Linux is already working on a bunch of 68000
    machines and I just need to get everything a little bit smaller
    to get into 4MB of RAM.

Signed-off-by: Daniel Palmer <daniel@thingy.jp>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2026-05-29 20:57:52 +02:00
Julien Olivain
ddce0814a7 arch: mark a set of target configurations as secondary
Those target configurations marked as "secondary" will be tested with a
lower probability in autobuilders. The intent is to focus the Buildroot
development (and bugfixes) on mainstream configurations, while still
keeping some other, less common, configurations.

This commit marks the following CPU architectures as secondary:

BR2_arcle (ARC little endian)
BR2_armeb (ARM big endian)
BR2_aarch64_be (AArch64 big endian)
BR2_hppa (PA-RISC)
BR2_loongarch64
BR2_m68k
BR2_microblazeel (Microblaze AXI, little endian)
BR2_microblazebe (Microblaze non-AXI, big endian)
BR2_mips (MIPS, big endian)
BR2_mipsel (MIPS, little endian)
BR2_mips64 (MIPS64 big endian)
BR2_or1k (OpenRISC)
BR2_powerpc (PowerPC, big endian)
BR2_powerpc64 (PowerPC64, big endian)
BR2_s390x
BR2_sh (SuperH)
BR2_sparc
BR2_sparc64
BR2_xtensa

In the following CPU architecture, only specific configurations are
marked secondary:

In BR2_armeb (ARM little endian),
- armv4 cores (arm920t, arm922t, fa526/626, strongarm sa110/sa1100)

In BR2_riscv:
- all 32-bit configurations
- 64-bit no-MMU

In BR2_i386 (x86 32-bit),
- i486, i586 and X1000 CPU

There was no strict rule established to build this list of secondary
configurations. This list was built mainly from the observation of
which architecture/CPUs are still widely used in the field
(disregarding its age), the quality of their upstream support and
the general relevance in the Buildroot project.

Signed-off-by: Julien Olivain <ju.o@free.fr>
[Arnout: use !BR2_HIDE_SECONDARY_TARGET_OPTIONS instead of
BR2_SHOW_SECONDARY_TARGET_OPTIONS]
Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
2026-04-07 21:46:43 +02:00
Julien Olivain
ed283567a8 arch/Config.in.x86: increase x86 default CPU from i586 to i686
Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
2026-04-07 21:25:36 +02:00
Julien Olivain
3dbb2a0aaa arch/arm: add the Neoverse-V3AE core
This commit adds the Neoverse-V3AE (Automotive Enhanced) core, which
is an armv9.2a ISA. See: [1] [2].

This CPU support was added in GCC 15. See [3] [4] [5].

This CPU supports Aarch64 only at all exception levels (EL0 to EL3).

This CPU is present in NVIDIA Jetson Thor / Tegra T264 [6].

Note: at the time of this commit, the latest binutils v2.46 does not
include a Neoverse-V3AE support for its '-mcpu' option. See [7]. This is
not an issue because gcc will call the "as" assembler with the relevant
"-march=armv9.2-a+EXTENSION..." options. Binutils supports "armv9.2-a"
since upstream commit [8] (first included in 2.38), and the oldest
Binutils version in Buildroot is 2.44.

[1] https://developer.arm.com/Processors/Neoverse%20V3AE
[2] https://developer.arm.com/documentation/101595/0002/The-Neoverse-V3AE--core/Neoverse-V3AE--core-features
[3] https://gcc.gnu.org/gcc-15/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-15.1.0#l222
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=7ca2a803c4a0d8e894f0b36625a2c838c54fb4cd
[6] https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-thor/
[7] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/config/tc-aarch64.c;h=cd76163488c48e45d43c35b2704d637999d51015;hb=3e93b95c3ae3f00a0283ddbab8029cbc07d96aff#l10833
[8] https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=3518022233e6b757c57d3deb7723fd91214fe036

Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-03-13 21:52:31 +01:00
Julien Olivain
7e75792675 arch/arm: add the Neoverse-V3 core
This commit adds the Neoverse-V3 core, which is an armv9.2a ISA.
See: [1] [2].

This CPU support was added in GCC 15. See [3] [4] [5].

This CPU supports Aarch64 only at all exception levels (EL0 to EL3).

Note: at the time of this commit, the latest binutils v2.46 does not
include a Neoverse-V3 support for its '-mcpu' option. See [6]. This is
not an issue because gcc will call the "as" assembler with the relevant
"-march=armv9.2-a+EXTENSION..." options. Binutils supports "armv9.2-a"
since upstream commit [7] (first included in 2.38), and the oldest
Binutils version in Buildroot is 2.44.

[1] https://developer.arm.com/Processors/Neoverse%20V3
[2] https://developer.arm.com/documentation/107734/0002/The-Neoverse--V3--core/Neoverse--V3--core-features
[3] https://gcc.gnu.org/gcc-15/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-15.1.0#l221
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=729000b90300a31ef9ed405635a0be761c5e168b
[6] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/config/tc-aarch64.c;h=cd76163488c48e45d43c35b2704d637999d51015;hb=3e93b95c3ae3f00a0283ddbab8029cbc07d96aff#l10833
[7] https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=3518022233e6b757c57d3deb7723fd91214fe036

Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-03-13 21:52:31 +01:00
Julien Olivain
efe7aa7ca4 arch/arm: add the Neoverse-V2 core
This commit adds the Neoverse-V2 core, which is an armv9.0a ISA.
See: [1] [2].

This CPU support was added in GCC 13. See [3] [4] [5].

This CPU supports Aarch64 at all exception levels (EL0 to EL3).
It also supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code. GCC has the support
to do so. Since Buildroot recompiles a full system (ATF, Kernel,
user-space) this support has limited value. This is why this
CPU is limited to 64bit builds only.

Note: at the time of this commit, the latest binutils v2.46 does not
include a Neoverse-V2 support for its '-mcpu' option. See [6]. This is
not an issue because gcc will call the "as" assembler with the relevant
"-march=armv9-a+EXTENSION..." options. Binutils supports "armv9-a"
since upstream commit [7] (first included in 2.38), and the oldest
Binutils version in Buildroot is 2.44.

[1] https://developer.arm.com/Processors/Neoverse%20V2
[2] https://developer.arm.com/documentation/102375/latest/
[3] https://gcc.gnu.org/gcc-13/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-13.1.0#l184
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=14d4b4fb12041dde1511262b926662929196c3fe
[6] https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/config/tc-aarch64.c;h=cd76163488c48e45d43c35b2704d637999d51015;hb=3e93b95c3ae3f00a0283ddbab8029cbc07d96aff#l10833
[7] https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=d5007f0280d881a8add44e6a68a3f536e138244c

Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-03-13 21:52:31 +01:00
Julien Olivain
99d6268223 arch/arm: add the Neoverse-V1 core
This commit adds the Neoverse-V1 core, which is an armv8.4a ISA.
See: [1] [2].

This CPU support was added in GCC 11. See [3] [4] [5].

This CPU supports Aarch64 at all exception levels (EL0 to EL3).
It also supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code. GCC has the support
to do so. Since Buildroot recompiles a full system (ATF, Kernel,
user-space) this support has limited value. This is why this
CPU is limited to 64bit builds only.

Qemu added neoverse-v1 support in upstream commit [6], first included
in v8.1.0.

[1] https://developer.arm.com/Processors/Neoverse%20V1
[2] https://developer.arm.com/documentation/101427/0102/Functional-description/Introduction/About-the-core
[3] https://gcc.gnu.org/gcc-11/changes.html#arm-targets
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-11.1.0#l141
[5] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c9d56eb777552ac5ee0c281e1f6e34b6fe929b77
[6] c74138c6c0

Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-03-13 21:52:31 +01:00
Charlie Jenkins
166bfd3e66 arch: riscv: Add RISCV_ISA_EXTRA config string
Adds a new user-configurable string to arch/Config.in.riscv, and in
arch/arch.mk.riscv appends it to GCC_TARGET_ARCH.

This enables custom extensions/combinations to be easily configured.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Arnout:
 - fix check-package warnings
 - introduce ARCH_RISV_ISA_EXTRA to simplify stripping of quotes
]
Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
2026-02-04 11:11:43 +01:00
Vincent Stehlé
1822f07e94 package/glibc: enable hppa support
Add support for HPPA.

Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Romain Naour <romain.naour@gmail.com>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-02-02 16:21:47 +01:00
Vincent Stehlé
3d1b77f98a arch/hppa: add new architecture
Add support for the Precision Architecture (a.k.a. PA-RISC),
a 32-bit architecture developed by Hewlett Packard.

While at it, add this arch to myself in DEVELOPERS.

Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Cc: Romain Naour <romain.naour@gmail.com>
Cc: Julien Olivain <ju.o@free.fr>
[Julien: arch "arch/" prefix in commit title]
Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-02-02 16:21:03 +01:00
Peter Korsgaard
f7447c0d86 arch/Config.in.arc: fix 'operations' typo
Found by codespell.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2026-01-21 19:13:47 +01:00
Thomas Petazzoni
2d570f8369 arch: drop support for ARC big-endian
Alexey Brodkin from Synopsys says in [1]:

  I think indeed, we may remove all the big-endian support for ARC.
  Reasons are since introduction of ARC HS4x processors we no longer
  support big-endian in any new processor IP, and even for older IP
  which used to support big-endian it was rarely used... so basically
  there's no good justification to spend any cycles on big-endian
  support looking forward in this project.  I.e. BE support in uClibc
  could also be removed if it makes any difference.

Therefore, let's removed support for ARC big-endian.

[1] https://lore.kernel.org/buildroot/SJ2PR12MB818487232470DA4456967C73A1A3A@SJ2PR12MB8184.namprd12.prod.outlook.com/

Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: ARC Maintainers <arc-buildroot@synopsys.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Reviewed-by: Maxim Kochetkov <fido_max@inbox.ru>
[Julien:
 - move legacy option to 2026.02 section
 - add link to mailing list
 - remove BR2_arceb from pkg-meson.mk to fix check-symbols error
]
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-12-13 17:39:02 +01:00
Edgar Bonet
36eed021b6 arch/Config.in.arm: fix typo in help text
Signed-off-by: Edgar Bonet <bonet@grenoble.cnrs.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-08-26 22:00:25 +02:00
Jiaxun Yang
bc28c3df6f arch/loongarch: Mark lp64f and lp64s as broken
Toolchain failed to bootstrap with LP64F and LP64S ABIs.

As reported by Julien in [1]:

Testing the "lp64f" ABI with commands:

     cat >.config <<EOF
     BR2_loongarch64=y
     BR2_LOONGARCH_FPU_32=y
     BR2_LINUX_KERNEL=y
     BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
     BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
     BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
     BR2_TARGET_ROOTFS_EXT2=y
     # BR2_TARGET_ROOTFS_TAR is not set
     EOF
     make olddefconfig
     make

fails in host-gcc-initial with output:

     Assembler messages:
     /tmp/ccEkwSsD.s:28: Error: register save offset not a multiple of 8
     /tmp/ccEkwSsD.s:30: Error: register save offset not a multiple of 8
     /tmp/ccEkwSsD.s:50: Error: register save offset not a multiple of 8

See also autobuilder failures such as [2].

Testing the "lp46s" ABI with commands:

     cat >.config <<EOF
     BR2_loongarch64=y
     BR2_LOONGARCH_FPU_NONE=y
     BR2_LINUX_KERNEL=y
     BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG=y
     BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
     BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y
     BR2_TARGET_ROOTFS_EXT2=y
     # BR2_TARGET_ROOTFS_TAR is not set
     EOF
     make olddefconfig
     make

fails in host-gcc-final with output:

     /buildroot/output/host/loongarch64-buildroot-linux-gnusf/bin/ld: cannot find crti.o: No such file or directory
     /buildroot/output/host/loongarch64-buildroot-linux-gnusf/bin/ld: cannot find -lc: No such file or directory
     /buildroot/output/host/loongarch64-buildroot-linux-gnusf/bin/ld: cannot find crtn.o: No such file or directory

See also autobuilder failures with as [3].

This commit marks those ABIs as broken at the moment to allow time
for investigation. Also, since gcc defaults to the "lp64d" ABI which
requires a 64bit FPU is present, the BR2_LOONGARCH_FPU_32 and
BR2_LOONGARCH_FPU_NONE options also needs to be marked as broken
as well. See [4].

[1] https://lore.kernel.org/buildroot/e17da108d1fb4e6abda26445dc053b35@free.fr/
[2] https://autobuild.buildroot.org/results/f98570293823867e6c43a1672e1a4b43ca1e4be5
[3] https://autobuild.buildroot.org/results/cf56c37fabcae964dbf4f96eb43a7e4d964452b6
[4] https://lore.kernel.org/buildroot/7b0f1cb629fce8a57d9b644b8beb8b2a@free.fr/

Cc: Mingcong Bai <jeffbai@aosc.io>
Cc: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[Julien:
 - add link to mailing list discussion
 - add configuration to reproduce issues to help future investigations
 - add links to autobuilder failures in commit log
 - mark BR2_LOONGARCH_FPU_{32,NONE} as broken
]
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-08-09 18:22:21 +02:00
Jiaxun Yang
9431681402 arch/loongarch: Fix minimal GCC version for target arch options
As reported by Thomas in [1], autobuilders reported host-gcc-initial
failures at configure time, with message:

    Unknown arch in --with-arch=la64v1.0

Both la64v1.0 and la64v1.1 requires GCC 14 as minimum, introduced in
upstream commit [2].

[1] https://lore.kernel.org/buildroot/20250709225522.0a12e583@windsurf/
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b4ebdd153b2b068082b452772095260b03b78cc2

Fixes: https://autobuild.buildroot.org/results/04a904f08d6e0aacbd308692c99e77a334d72b95/
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[Julien:
 - add links to mailing list and upstream commit
 - remove unrelated comment change to previous commit
]
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-07-12 12:40:13 +02:00
Julien Olivain
279cd77865 arch/loongarch: add lsx/lasx SIMD dependency on fpu64
Since the LoongArch64 introduction in commit [1], the Kconfig menus
allows selecting lsx and lasx SIMD options independently of the FPU
configuration.

When lsx or lasx SIMD is selected and FPU is "none", host-gcc-initial
is failing at configuration time, with error:

    --with-simd=lasx conflicts with --with-fpu=none

According to the gcc configuration script [2], lsx and lasx values
are valid only if FPU is 64.

This commit adds the missing "depends on BR2_LOONGARCH_FPU_64" for
BR2_LOONGARCH_SIMD_LSX and BR2_LOONGARCH_SIMD_LASX options.

Fixes:
https://autobuild.buildroot.org/results/d159645dab9206dd46f45e79241fc8a950bd0326/

[1] 54895db9c1
[2] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config.gcc;h=a6f6efec4e103301225ef74c2d1159933d1c9cf8;hb=1757c320badc92c0628eafcd07d54585659692ed#l5163

Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-07-07 18:45:59 +02:00
Jiaxun Yang
5495bdd430 package/glibc: Enable LoongArch64 support
Glibc introduced LoongArch64 support in 2.36, it requires kernel
5.19 to build.

Unselect BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT to reflect we can
build the toolchain.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Romain Naour <romain.naour@smile.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-07-05 19:45:38 +02:00
Jiaxun Yang
54895db9c1 arch: Introduce LoongArch64
Introduce LoongArch64 at architecture level.

Config.in.loongarch is prepared for possible loongarch32
enablement in future, thus BR2_ARCH_IS_64 is being depended
by some 64bit only options.

Internal toolchain is supported, as our minimal binutils
version is already beyond LoongArch minimal version and
GCC option is limited by BR2_ARCH_NEEDS_GCC_AT_LEAST_12.

BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT is selected temporary
and it's going to be rmoved after we gain libc support.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[Julien: fix typo in Kconfig BR2_LOONGARCH_ABI_LP64S prompt
  replace "lp64d" by "lp64s"]
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-07-05 19:45:38 +02:00
Jiaxun Yang
286f5bacd7 package/gcc: Introduce BR2_GCC_TARGET_SIMD option
Introduce BR2_GCC_TARGET_SIMD for gcc to handle --with-simd/-msimd
present at loongarch's gcc options.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Romain Naour <romain.naour@smile.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-07-05 19:45:38 +02:00
Julien Olivain
7724268034 arch/Config.in: introduce BR2_ARCH_NEEDS_GCC_AT_LEAST_16
gcc 15 was introduced in Buildroot in commit [1].

In Buildroot, a user creates a build configuration in Kconfig
menus by selecting the CPU architecture and CPU first, then
a toolchain that support this CPU, then packages and system
configuration.

To make sure those Kconfig menus and choices behave correctly in that
order, we use a logic in which a CPU selects the Kconfig symbol
BR2_ARCH_NEEDS_GCC_AT_LEAST_N (with N being the needed gcc version).
Then, to make sure unsupported gcc version are hidden for a selected
CPU, a gcc version N has in fact a "depends on
!BR2_ARCH_NEEDS_GCC_AT_LEAST_(N+1)". For example, Cortex-A710 needs
at least gcc 12. See [2] and [3].

This means that when we introduce the latest gcc version with this
logic in place, we already need this BR2_ARCH_NEEDS_GCC_AT_LEAST_(N+1)
symbol defined. Doing so is desirable to avoid forgetting to add it
later. See for example commit [4], adding those missing dependencies
for gcc 13 and 14.

Since in Buildroot we currently keep 3 actively maintained gcc
versions, adding a new gcc version N in Buildroot should:
- add the BR2_ARCH_NEEDS_GCC_AT_LEAST_(N+1) symbol
- add package/gcc N
- switch the default gcc from N-2 to N-1
- drop package/gcc N-3

Then, once this new gcc N is added, new CPUs supported by that version
can be introduced, by selecting BR2_ARCH_NEEDS_GCC_AT_LEAST_N.

All this logic will be ready for future gcc versions. This was also
described in commit log [5].

This commit simply adds the BR2_ARCH_NEEDS_GCC_AT_LEAST_16 symbol.

It is worth mentioning that, at the time of this commit, gcc 16 is not
released yet. This release number 16 is already known, though. See [6].

For reference, this was discussed in [7].

[1] 75891397ab
[2] https://gitlab.com/buildroot.org/buildroot/-/blob/2025.05/arch/Config.in.arm#L514
[3] https://gitlab.com/buildroot.org/buildroot/-/blob/2025.05/package/gcc/Config.in.host#L27
[4] 6f231d3003
[5] eab17d763c
[6] https://gcc.gnu.org/gcc-16/changes.html
[7] https://lore.kernel.org/buildroot/877c0v1sn1.fsf@dell.be.48ers.dk/T/#m45688e25632401029e4c0d989072e1d3e1a59854

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Romain Naour <romain.naour@smile.fr>
2025-07-02 15:14:45 +02:00
Julien Olivain
de374e06d8 arch/arm: add the Cortex-A720 core
This commit adds the Cortex-A720 core, which is a armv9.2a ISA.
See: [1] [2].

This CPU support was added in GCC 14. See [3] [4].

Cortex-A720 processors are included in boards such as the
Radxa Orion O6. See [5].

This CPU supports Aarch64 only at all exception levels (EL0 to EL3).

[1] https://developer.arm.com/Processors/Cortex-A720
[2] https://developer.arm.com/documentation/102530/0002/The-Cortex-A720--core/Cortex-A720--core-features
[3] https://gcc.gnu.org/gcc-14/changes.html#aarch64
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-14.1.0#l180
[5] https://radxa.com/products/orion/o6/

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2025-05-30 21:31:37 +02:00
Julien Olivain
c39f677e6a arch/arm: add the Cortex-A710 core
This commit adds the Cortex-A710 core, which is an implementation of
the armv9.0a ISA. See: [1] [2].

This CPU support was added in GCC 12. See [3] [4].

Cortex-A710 support has been added in QEmu in commit [5], first
included in v8.2.0.

This CPU supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code targeting. GCC has the
support to do so. Since Buildroot recompiles a full system (ATF,
Kernel, user-space) this support has limited value. This is why this
CPU is limited  to 64bit builds only.

[1] https://developer.arm.com/Processors/Cortex-A710
[2] https://developer.arm.com/documentation/101800/0201/The-Cortex-A710--core/Cortex-A710--core-features
[3] https://gcc.gnu.org/gcc-12/changes.html
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-12.1.0#l163
[5] e3d45c0a89

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2025-02-05 11:43:43 +01:00
Julien Olivain
9845bd4541 arch/arm: add Armv9-A and the Neoverse N2 core
This commit adds the Neoverse N2 core, which is an implementation of
the armv9.0a ISA. See: [1] [2].

This CPU support was added in GCC 11. See [3].

The Neoverse N2 CPU is included in the Arm sbsa-ref platform in Qemu.
The Armv9.0-A Buildroot support will be needed to update those SBSA
related components. See the note in commit log [4].

This commit introduces the BR2_ARM_CPU_ARMV9A Kconfig symbol, which just
selects BR2_ARM_CPU_ARMV8A. This is because Armv9.0-A is a superset of
Armv8.5-A. This symbol can help package recipes to detect this new base
architecture.

Neoverse-N2 support has been added in QEmu in commit [5], first
included in v8.2.0.

This CPU supports Aarch32 only in EL0 (user-space). This means it's
technically possible to compile Aarch32 code targeting it. GCC has
the support to do so. Since Buildroot recompiles a full system (ATF,
Kernel, user-space) this support has limited value. This is why this
CPU is limited to 64bit builds only.

[1] https://developer.arm.com/Processors/Neoverse%20N2
[2] https://developer.arm.com/documentation/102099/0003/The-Neoverse-N2--core/Neoverse-N2--core-features
[3] https://gcc.gnu.org/gcc-11/changes.html
[4] c58a2a9687
[5] dfff1000fe

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2025-02-05 11:43:30 +01:00
Romain Naour
6775ccc5a1 arch/nios2: drop architecture
The nios2 architecture was deprecated in gcc-14 and has been removed
in the upcoming gcc-15 [1][2].

This commit removes nios2 from the architecture entry.

[1] https://sourceware.org/pipermail/binutils/2024-April/133675.html
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=e876acab6cdd84bb2b32c98fc69fb0ba29c81153

Signed-off-by: Romain Naour <romain.naour@smile.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-01-15 21:30:52 +01:00
Romain Naour
3cc2fef0d2 arch: disable nios2
The nios2 architecture was deprecated in gcc-14 and has been removed
in the upcoming gcc-15 [1][2].

Our last and only nios2 defconfig "qemu_nios2_10m50_defconfig" was
removed in 2024.11 due to nios2 removal from Qemu 9.1.0 [3].

This patch only definitively hides the symbol. When all references
to it are removed (to come in followup patches), we'll eventually
remove the symbol altogether.

[1] https://sourceware.org/pipermail/binutils/2024-April/133675.html
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=e876acab6cdd84bb2b32c98fc69fb0ba29c81153
[3] f96b4c176f

Signed-off-by: Romain Naour <romain.naour@smile.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-01-15 21:30:31 +01:00
Romain Naour
5cb7e4ad3d package/glibc: remove nios2 support
Doing so, we remove nios2 support from the internal toolchain backend.

Signed-off-by: Romain Naour <romain.naour@smile.fr>
Signed-off-by: Julien Olivain <ju.o@free.fr>
2025-01-15 21:30:23 +01:00
Julien Olivain
f4690c2bfd arch/arm: add the Cortex-A78 core
This commit adds the Cortex-A78 core, which is a armv8.2a ISA.
See: [1] [2].

This CPU support was added in GCC 11. See [3] [4].

Buildroot commit 771da1dd9 "configs/nvidia_bf3_defconfig: new
defconfig" [5] added the first defconfig for a board including
this CPU.

[1] https://developer.arm.com/Processors/Cortex-A78
[2] https://developer.arm.com/documentation/101430/0102/Functional-description/Introduction/About-the-core
[3] https://gcc.gnu.org/gcc-11/changes.html
[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64-cores.def;hb=releases/gcc-11.1.0#l98
[5] 771da1dd9b

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-12-29 22:51:22 +01:00
Ben Wolsieffer
d75e29c9b2 arch/arm: add support for FDPIC
Linux on ARM supports FDPIC binaries intended for use on no-MMU
systems. This patch enables support for building a toolchain that
produces FDPIC binaries, only for ARMv7-M platforms, for which FDPIC
binaries are relevant.

The target name for a FDPIC toolchain must be
arm-<vendor>-uclinuxfdpiceabi, which doesn't follow the standard
format and requires a special case.

Signed-off-by: Ben Wolsieffer <Ben.Wolsieffer@hefring.com>
Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-10-02 22:34:13 +02:00
Ben Wolsieffer
66e8b5ece4 arch: don't enable FDPIC binaries by default
FDPIC support is being added as a new option for an existing
architecture (ARM), so we don't want to suddenly change the default.

Signed-off-by: Ben Wolsieffer <Ben.Wolsieffer@hefring.com>
Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-10-02 22:20:44 +02:00
Ben Wolsieffer
45c0a5114d Revert: "arch: drop now useless support for FDPIC"
This reverts commit 58dcd28dfb.

ARM supports FDPIC, so this code is needed once again.

Signed-off-by: Ben Wolsieffer <Ben.Wolsieffer@hefring.com>
Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-10-02 22:20:43 +02:00
Yann E. MORIN
2ba879cc38 arch/Config.in.arc: fix indentation
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2024-09-07 19:18:33 +02:00
Daniel Palmer
a1a638f14c arch/Config.in.m68k: Add an option for 68030
Buildroot is probably the only thing lightweight enough to run on
68030 machines in the current day.

Add a CPU option for the 68030.

Tested on a Motorola MVME147.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-09-03 22:38:09 +02:00
Thomas Petazzoni
f577d8218f arch/Config.in: introduce BR2_ARCH_NEEDS_GCC_AT_LEAST_15
Since we're going to introduce external toolchains that are based on
GCC 14.x, we will need them to "depends on
!BR2_ARCH_NEEDS_GCC_AT_LEAST_15", so let's introduce this symbol
first.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2024-09-03 22:01:48 +02:00
Thomas Petazzoni
01becc082d arch/Config.in.x86: drop knightslanding and knightsmill archs
According to the GCC 14.x release notes at
https://gcc.gnu.org/gcc-14/changes.html:

  Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are
  marked as deprecated. GCC will emit a warning when using the
  -mavx5124fmaps, -mavx5124vnniw, -mavx512er, -mavx512pf,
  -mprefetchwt1, -march=knl, -march=knm, -mtune=knl or -mtune=knm
  compiler switches. Support will be removed in GCC 15.

Using those architectures already emits warnings, which when treated
as errors cause build failures, such as:

  cc1: error: '-march=knm' support will be removed in GCC 15 [-Werror=deprecated]
  cc1: all warnings being treated as errors

Therefore, let's drop support for those two architectures, which are
anyway not common at all, especially in the embedded space.

Fixes:

  http://autobuild.buildroot.net/results/ce98c41b22212f52bf7b53d84871b8e03409dbca/

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-07-30 09:29:22 +02:00
Waldemar Brodkorb
e32d404f6c arch: allow riscv32 noMMU configuration
Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-05-12 12:19:18 +02:00
Stefan Ott
4c561a7adf arch/Config.in.x86: enable SSE2 on Pentium M
The Pentium M does support SSE2 so it would make sense to enable it.

Signed-off-by: Stefan Ott <stefan@ott.net>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-05-12 12:05:53 +02:00
Waldemar Brodkorb
5cfda60060 arch: remove BINFMT_FLAT_SHARED support
BINFMT_FLAT_SHARED was removed in the Linux Kernel by commit:
70578ff3367dd4ad8f212a9b5c05cffadabf39a8

It was m68k specific and got recently disabled in uClibc-ng, too.
See this commit:
https://cgit.uclibc-ng.org/cgi/cgit/uclibc-ng.git/commit/?id=72b01dd20f9cea273809e3437b4aba849ae658af

Now that only BINFMT_FLAT_ONE is supported, remove the choice entirely.

BINFMT_FLAT_SEP_DATA was removed in 2018 from Buildroot by commit:
e2ea4157a9

Signed-off-by: Waldemar Brodkorb <wbx@openadk.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-05-11 22:17:46 +02:00
Dmitry Chestnykh
6db46a6785 arch/Config.in: allow building a buildroot toolchain on SPARC
With this patch series we again allow building a Buildroot toolchain
for SPARC, because SPARC was fixed in uClibc-ng, so SPARC systems
work fine now.

Signed-off-by: Dmitry Chestnykh <dm.chestnykh@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2024-05-06 22:38:03 +02:00
Gaël PORTAY
7a59c3a4d4 arch: add support 16k page size on ARM64
The BCM2712 of the RaspberryPi 5 supports for 16KB page size.

This adds support for 16 KB on ARM64.

Signed-off-by: Gaël PORTAY <gael.portay@rtone.fr>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2024-01-19 21:19:33 +01:00
Thomas Petazzoni
eab17d763c arch/Config.in: introduce BR2_ARCH_NEEDS_GCC_AT_LEAST_14
Since commit
a0d2a5cfec ("support/scripts/gen-bootlin-toolchains:
generate BR2_ARCH_NEEDS_GCC_AT_LEAST_X guard"), the
gen-bootlin-toolchains script will generate references to
BR2_ARCH_NEEDS_GCC_AT_LEAST_X including potentially against the "next"
version of gcc.

Indeed, a toolchain using gcc 13.x should have a "depends on
!BR2_ARCH_NEEDS_GCC_AT_LEAST_14" so that once some architectures that
require gcc 14.x are added, such toolchains are not made visible.

In order for this to work, we must have the
BR2_ARCH_NEEDS_GCC_AT_LEAST_x symbol ready for the N+1 version of gcc
compared to the latest one we support.

As we're supporting up to gcc 13.x right now, let's introduce the
symbol BR2_ARCH_NEEDS_GCC_AT_LEAST_14 so that gcc 13.x toolchains can
be marked depends on !BR2_ARCH_NEEDS_GCC_AT_LEAST_14.

The other alternative would be to make the gen-bootlin-toolchains a
bit smarter, and not emit this depends on
!BR2_ARCH_NEEDS_GCC_AT_LEAST_14 if BR2_ARCH_NEEDS_GCC_AT_LEAST_14 does
not exist. But this would require re-running the script when
BR2_ARCH_NEEDS_GCC_AT_LEAST_14 which we are unlikely to do. While
today, when the script is invoked, the usual check-symbols complains
and reminds us that BR2_ARCH_NEEDS_GCC_AT_LEAST_14 should be added, so
we remember to do it right away.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2023-12-28 21:57:44 +01:00
Yann E. MORIN
ebe2a113ab arch/powerpc: drop ABI selection
Since it was introduced in 5a6087d62e (toolchain: add powerpc SPE ABI
support), the CLASSIC vs. SPE choice for the ABI was never really a
choice: CPU without SPE could only use the CLASSIC ABI, while CPUs with
SPE could only use the SPE ABI.

Commit b4c824562b (powerpc: add BR2_POWERPC_CPU_HAS_SPE to replace
adhoc deps/checks) added a blind option that CPUs with SPE would select
rather than duplicate the ad-hoc dependencies in both CLASSIC and SPE
ABI options. Since then, it was even more obvious that the ABI choice
was really not a choice, as the two options have mutually exclusive
conditions.

Drop the useless choice, and directly use the blind option as selected
by the specific CPUs.

We don't need legacy handling, because the situation fixes itself.

Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
Cc: Joel Stanley <joel@jms.id.au>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-08-20 23:22:27 +02:00
Jamie Gibbons
cbd91e89e4 arch/Config.in.riscv: allow extensions for generic
The generic extension set 'G' is realy a base with the minimal set of
extensions needed to be comfortable (but not required) to run a
linux-bassed system. Similarly, we consider the custom to be about the
custom set of features (not about a custom core implementing such a
set).

As such, we allow that a core with the G set can have futher extensions
without requiring it to be configured as a custom set.

We drop the intermediate symbols with the prompts, and move the prompts
to the previously hidden symbols, and add a prompt for the I set.

This alows one to clearly see what the generic set is about, without
having to delve into the help and hunt the list of selected symbol.

Note however that the G set implies Zicsr and Zifencei, but we have no
prompt for thos two, because in Buildroot, we assume that they are
mandatory and always present, like the I set (which they previously were
part of).

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
[yann.morin.1998@free.fr:
  - drop the intermediate symbols
  - move prompt to previously hidden symbols
  - add symbol for I
  - update defconfigs
  - reword the commit log accordingly
]
Signed-off-by: Yann E. MORIN <yann.morin.1998@free.fr>
2023-08-18 23:45:45 +02:00
Florian Fainelli
60cf00d3f4 arch/mips: re-add support for MIPS IV
Support for MIPS IV was dropped in commit
dd45fe0efb ("arch/mips: remove
deprecated mips1/2/3/4 support"). However, even though it is an older
ISA than R1, it is still useful to support older MIPS-based
systems (e.g.: Cobalt Qube).

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-08-10 22:39:10 +02:00
Vincent Fazio
2bd0431baf arch/Config.in.x86: consolidate Geode CPU targets
Since its introduction in 7d8a59b40, the BR2_x86_geode CPU target has
pointed to GCC -march=geode which targets AMD Geode processors [0].

This arch tuning enables MMX and 3DNow! extensions in GCC but these are
not currently reflected in the selected flags by BR2_x86_geode.

This is likely due to the confusing naming and history of "Geode".

The AMD Geode can trace its origins back to the Cyrix MediaGXm [1] and
then to the NSC Geode GXm/GXLV/GX1/GX2 [2]. All of these processors have
MMX instruction support listed in their datasheets. The NSC GX2 was the
first in the series to enable 3DNow!.

When 7fed07d3a4 introduced BR2_X86_CPU_HAS_MMX, Geode was skipped
presumably because it wasn't clear that the target is AMD Geode and
because the Wikipedia documentation for Geode is incomplete [2] with
regards to supported instructions as they all support MMX.

When f6cd56b9ce introduced BR2_X86_CPU_HAS_3DNOW, Geode was skipped
presumably for similar reasons.

Note: the in-tree olpc_xo1_defconfig uses BR2_x86_geode which is fine
as this hardware uses the AMD Geode [3].

Make it more clear that the target is AMD Geode by renaming the Kconfig
menu option and add both MMX and 3DNow! flags to BR2_x86_geode.

This also means that BR2_x86_geode_mmx is no longer needed, and can be
removed. No legacy handling is needed since BR2_x86_geode_mmx has
never been part of any release.

[0]: https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/i386/geode.md;;hb=HEAD
[1]: https://en.wikipedia.org/wiki/MediaGX#MediaGXm
[2]: https://en.wikipedia.org/wiki/Geode_%28processor%29
[3]: https://wiki.laptop.org/go/Hardware_specification

Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-08-01 23:16:02 +02:00
Vincent Fazio
22e476d788 arch/Config.in.x86: add Intel and AMD GCC targets
Sync the Intel and AMD CPU target list with GCC 13.

Multiple references are used for flags and synonyms [0] [1] [2] [3].

For Intel:
  Add Ivy Bridge, Sierra Forest, Grand Ridge, Knights Landing, Knights
  Mill, Granite Rapids, and Granite Rapids-D.

  The Sapphire Rapids CPU target supports Emerald Rapids.
  The Alder Lake CPU target supports Raptor Lake and Meteor Lake.

  Note: Knights Landing/Mills are based on Xeon Phi and do support
  some AVX512 extensions, but not the full subset required by
  BR2_X86_CPU_HAS_AVX512

For AMD:
  Add Bobcat, Bulldozer, Piledriver, Excavator, and Zen 1-4.

Add a comment to BR2_X86_CPU_HAS_AVX512 to explain the expected
extensions supported by the CPU. This flag was first selected by
skylake-avx512 and encompasses what appears to be a standard subset
across CPUs [3] and chapter 3 of the x86-64 psABI [4]:
  AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL

CPUs selecting this flag should, at a minimum, support this subset of
AVX512 extensions.

[0]: https://gcc.gnu.org/onlinedocs/gcc-13.2.0/gcc/x86-Options.html
[1]: https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/i386/i386.h;hb=refs/tags/releases/gcc-13.2.0
[2]: https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/common/config/i386/i386-common.cc;hb=refs/tags/releases/gcc-13.2.0
[3]: https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512
[4]: https://gitlab.com/x86-psABIs/x86-64-ABI/-/raw/master/x86-64-ABI/low-level-sys-info.tex

Signed-off-by: Vincent Fazio <vfazio@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2023-08-01 00:14:50 +02:00