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arch: mark a set of target configurations as secondary

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Those target configurations marked as "secondary" will be tested with a
lower probability in autobuilders. The intent is to focus the Buildroot
development (and bugfixes) on mainstream configurations, while still
keeping some other, less common, configurations.

This commit marks the following CPU architectures as secondary:

BR2_arcle (ARC little endian)
BR2_armeb (ARM big endian)
BR2_aarch64_be (AArch64 big endian)
BR2_hppa (PA-RISC)
BR2_loongarch64
BR2_m68k
BR2_microblazeel (Microblaze AXI, little endian)
BR2_microblazebe (Microblaze non-AXI, big endian)
BR2_mips (MIPS, big endian)
BR2_mipsel (MIPS, little endian)
BR2_mips64 (MIPS64 big endian)
BR2_or1k (OpenRISC)
BR2_powerpc (PowerPC, big endian)
BR2_powerpc64 (PowerPC64, big endian)
BR2_s390x
BR2_sh (SuperH)
BR2_sparc
BR2_sparc64
BR2_xtensa

In the following CPU architecture, only specific configurations are
marked secondary:

In BR2_armeb (ARM little endian),
- armv4 cores (arm920t, arm922t, fa526/626, strongarm sa110/sa1100)

In BR2_riscv:
- all 32-bit configurations
- 64-bit no-MMU

In BR2_i386 (x86 32-bit),
- i486, i586 and X1000 CPU

There was no strict rule established to build this list of secondary
configurations. This list was built mainly from the observation of
which architecture/CPUs are still widely used in the field
(disregarding its age), the quality of their upstream support and
the general relevance in the Buildroot project.

Signed-off-by: Julien Olivain <ju.o@free.fr>
[Arnout: use !BR2_HIDE_SECONDARY_TARGET_OPTIONS instead of
BR2_SHOW_SECONDARY_TARGET_OPTIONS]
Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
This commit is contained in:
Julien Olivain
2026-03-07 19:07:11 +01:00
committed by Arnout Vandecappelle
parent 4642f903cd
commit ddce0814a7
4 changed files with 29 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/Config.in
View File

@@ -23,6 +23,7 @@ choice
config BR2_arcle
bool "ARC (little endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
Synopsys' DesignWare ARC Processor Cores are a family of
@@ -41,6 +42,7 @@ config BR2_arm
config BR2_armeb
bool "ARM (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
ARM is a 32-bit reduced instruction set computer (RISC)
@@ -59,6 +61,7 @@ config BR2_aarch64
config BR2_aarch64_be
bool "AArch64 (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARCH_IS_64
help
Aarch64 is a 64-bit architecture developed by ARM Holdings.
@@ -67,6 +70,7 @@ config BR2_aarch64_be
config BR2_hppa
bool "HPPA"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
Precision Architecture (a.k.a. PA-RISC) is a 32-bit
@@ -82,6 +86,7 @@ config BR2_i386
config BR2_loongarch64
bool "LoongArch64"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
select BR2_ARCH_IS_64
select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
@@ -92,6 +97,7 @@ config BR2_loongarch64
config BR2_m68k
bool "m68k"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
# MMU support is set by the subarchitecture file, arch/Config.in.m68k
help
Motorola 68000 family microprocessor
@@ -99,6 +105,7 @@ config BR2_m68k
config BR2_microblazeel
bool "Microblaze AXI (little endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
@@ -108,6 +115,7 @@ config BR2_microblazeel
config BR2_microblazebe
bool "Microblaze non-AXI (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
@@ -117,6 +125,7 @@ config BR2_microblazebe
config BR2_mips
bool "MIPS (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Big
@@ -126,6 +135,7 @@ config BR2_mips
config BR2_mipsel
bool "MIPS (little endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
MIPS is a RISC microprocessor from MIPS Technologies. Little
@@ -135,6 +145,7 @@ config BR2_mipsel
config BR2_mips64
bool "MIPS64 (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
@@ -155,6 +166,7 @@ config BR2_mips64el
config BR2_or1k
bool "OpenRISC"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
OpenRISC is a free and open processor for embedded system.
@@ -162,6 +174,7 @@ config BR2_or1k
config BR2_powerpc
bool "PowerPC"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
PowerPC is a RISC architecture created by Apple-IBM-Motorola
@@ -171,6 +184,7 @@ config BR2_powerpc
config BR2_powerpc64
bool "PowerPC64 (big endian)"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
@@ -201,6 +215,7 @@ config BR2_riscv
config BR2_s390x
bool "s390x"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
@@ -210,6 +225,7 @@ config BR2_s390x
config BR2_sh
bool "SuperH"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
SuperH (or SH) is a 32-bit reduced instruction set computer
@@ -220,6 +236,7 @@ config BR2_sh
config BR2_sparc
bool "SPARC"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_USE_MMU
help
SPARC (from Scalable Processor Architecture) is a RISC
@@ -230,6 +247,7 @@ config BR2_sparc
config BR2_sparc64
bool "SPARC64"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARCH_IS_64
select BR2_USE_MMU
help
@@ -250,6 +268,7 @@ config BR2_x86_64
config BR2_xtensa
bool "Xtensa"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
help
Xtensa is a Tensilica processor IP architecture.

5
arch/Config.in.arm
View File

@@ -112,22 +112,27 @@ choice
if !BR2_ARCH_IS_64
comment "armv4 cores"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
config BR2_arm920t
bool "arm920t"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
config BR2_arm922t
bool "arm922t"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_THUMB
select BR2_ARM_CPU_ARMV4
config BR2_fa526
bool "fa526/626"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4
config BR2_strongarm
bool "strongarm sa110/sa1100"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_ARMV4

2
arch/Config.in.riscv
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@@ -58,10 +58,12 @@ choice
config BR2_RISCV_32
bool "32-bit"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
config BR2_RISCV_64
bool "64-bit"
select BR2_ARCH_IS_64
select BR2_RISCV_USE_MMU if BR2_HIDE_SECONDARY_TARGET_OPTIONS
endchoice

3
arch/Config.in.x86
View File

@@ -42,12 +42,15 @@ choice
config BR2_x86_i486
bool "i486"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
depends on !BR2_x86_64
config BR2_x86_i586
bool "i586"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
depends on !BR2_x86_64
config BR2_x86_x1000
bool "x1000"
depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
depends on !BR2_x86_64
help
The Intel X1000 is a Pentium class microprocessor in the