mirror of
https://gitlab.com/buildroot.org/buildroot.git
synced 2026-08-01 21:23:51 -09:00
ddce0814a7
Those target configurations marked as "secondary" will be tested with a lower probability in autobuilders. The intent is to focus the Buildroot development (and bugfixes) on mainstream configurations, while still keeping some other, less common, configurations. This commit marks the following CPU architectures as secondary: BR2_arcle (ARC little endian) BR2_armeb (ARM big endian) BR2_aarch64_be (AArch64 big endian) BR2_hppa (PA-RISC) BR2_loongarch64 BR2_m68k BR2_microblazeel (Microblaze AXI, little endian) BR2_microblazebe (Microblaze non-AXI, big endian) BR2_mips (MIPS, big endian) BR2_mipsel (MIPS, little endian) BR2_mips64 (MIPS64 big endian) BR2_or1k (OpenRISC) BR2_powerpc (PowerPC, big endian) BR2_powerpc64 (PowerPC64, big endian) BR2_s390x BR2_sh (SuperH) BR2_sparc BR2_sparc64 BR2_xtensa In the following CPU architecture, only specific configurations are marked secondary: In BR2_armeb (ARM little endian), - armv4 cores (arm920t, arm922t, fa526/626, strongarm sa110/sa1100) In BR2_riscv: - all 32-bit configurations - 64-bit no-MMU In BR2_i386 (x86 32-bit), - i486, i586 and X1000 CPU There was no strict rule established to build this list of secondary configurations. This list was built mainly from the observation of which architecture/CPUs are still widely used in the field (disregarding its age), the quality of their upstream support and the general relevance in the Buildroot project. Signed-off-by: Julien Olivain <ju.o@free.fr> [Arnout: use !BR2_HIDE_SECONDARY_TARGET_OPTIONS instead of BR2_SHOW_SECONDARY_TARGET_OPTIONS] Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
503 lines
12 KiB
Plaintext
503 lines
12 KiB
Plaintext
menu "Target options"
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config BR2_ARCH_IS_64
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bool
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config BR2_KERNEL_64_USERLAND_32
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bool
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config BR2_SOFT_FLOAT
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bool
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config BR2_USE_MMU
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bool
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config BR2_ARCH_HAS_FDPIC_SUPPORT
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bool
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choice
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prompt "Target Architecture"
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default BR2_i386
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help
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Select the target architecture family to build for.
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config BR2_arcle
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bool "ARC (little endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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Synopsys' DesignWare ARC Processor Cores are a family of
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32-bit CPUs that can be used from deeply embedded to high
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performance host applications. Little endian.
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config BR2_arm
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bool "ARM (little endian)"
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# MMU support is set by the subarchitecture file, arch/Config.in.arm
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help
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ARM is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by ARM Holdings.
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Little endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_armeb
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bool "ARM (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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ARM is a 32-bit reduced instruction set computer (RISC)
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instruction set architecture (ISA) developed by ARM Holdings.
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Big endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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config BR2_aarch64
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bool "AArch64 (little endian)"
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select BR2_ARCH_IS_64
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help
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Aarch64 is a 64-bit architecture developed by ARM Holdings.
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http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
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http://en.wikipedia.org/wiki/ARM
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config BR2_aarch64_be
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bool "AArch64 (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_ARCH_IS_64
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help
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Aarch64 is a 64-bit architecture developed by ARM Holdings.
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http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
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http://en.wikipedia.org/wiki/ARM
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config BR2_hppa
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bool "HPPA"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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Precision Architecture (a.k.a. PA-RISC) is a 32-bit
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(big endian) architecture developed by Hewlett Packard.
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https://en.wikipedia.org/wiki/PA-RISC
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config BR2_i386
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bool "i386"
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select BR2_USE_MMU
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help
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Intel i386 architecture compatible microprocessor
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http://en.wikipedia.org/wiki/I386
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config BR2_loongarch64
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bool "LoongArch64"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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select BR2_ARCH_IS_64
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
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help
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LoongArch64 is 64-bit architecture developed by Loongson.
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http://www.loongson.cn/
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https://en.wikipedia.org/wiki/Loongson
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config BR2_m68k
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bool "m68k"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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# MMU support is set by the subarchitecture file, arch/Config.in.m68k
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help
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Motorola 68000 family microprocessor
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http://en.wikipedia.org/wiki/M68k
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config BR2_microblazeel
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bool "Microblaze AXI (little endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
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bus based architecture (little endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_microblazebe
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bool "Microblaze non-AXI (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
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bus based architecture (non-AXI, big endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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config BR2_mips
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bool "MIPS (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mipsel
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bool "MIPS (little endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64
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bool "MIPS64 (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Big
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_mips64el
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bool "MIPS64 (little endian)"
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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MIPS is a RISC microprocessor from MIPS Technologies. Little
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endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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config BR2_or1k
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bool "OpenRISC"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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OpenRISC is a free and open processor for embedded system.
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http://openrisc.io
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config BR2_powerpc
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bool "PowerPC"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_powerpc64
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bool "PowerPC64 (big endian)"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_powerpc64le
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bool "PowerPC64 (little endian)"
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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PowerPC is a RISC architecture created by Apple-IBM-Motorola
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alliance. Little endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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config BR2_riscv
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bool "RISCV"
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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help
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RISC-V is an open, free Instruction Set Architecture created
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by the UC Berkeley Architecture Research group and supported
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and promoted by RISC-V Foundation.
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https://riscv.org/
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https://en.wikipedia.org/wiki/RISC-V
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config BR2_s390x
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bool "s390x"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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s390x is a big-endian architecture made by IBM.
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http://www.ibm.com/
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http://en.wikipedia.org/wiki/IBM_System/390
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config BR2_sh
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bool "SuperH"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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SuperH (or SH) is a 32-bit reduced instruction set computer
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(RISC) instruction set architecture (ISA) developed by
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Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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config BR2_sparc
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bool "SPARC"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_USE_MMU
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help
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SPARC (from Scalable Processor Architecture) is a RISC
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instruction set architecture (ISA) developed by Sun
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Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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config BR2_sparc64
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bool "SPARC64"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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SPARC (from Scalable Processor Architecture) is a RISC
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instruction set architecture (ISA) developed by Sun
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Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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config BR2_x86_64
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bool "x86_64"
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select BR2_ARCH_IS_64
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select BR2_USE_MMU
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help
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x86-64 is an extension of the x86 instruction set (Intel i386
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architecture compatible microprocessor).
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http://en.wikipedia.org/wiki/X86_64
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config BR2_xtensa
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bool "Xtensa"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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# MMU support is set by the subarchitecture file, arch/Config.in.xtensa
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help
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Xtensa is a Tensilica processor IP architecture.
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http://en.wikipedia.org/wiki/Xtensa
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http://www.tensilica.com/
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endchoice
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# For some architectures or specific cores, our internal toolchain
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# backend is not suitable (like, missing support in upstream gcc, or
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# no ChipCo fork exists...)
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config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
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bool
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config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
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bool
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default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
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# The following symbols are selected by the individual
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# Config.in.$ARCH files
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
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bool
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_8
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_10
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_10
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_12
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_13
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_14
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_13
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_15
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_14
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config BR2_ARCH_NEEDS_GCC_AT_LEAST_16
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bool
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
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# The following string values are defined by the individual
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# Config.in.$ARCH files
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config BR2_ARCH
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string
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config BR2_NORMALIZED_ARCH
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string
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config BR2_ENDIAN
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string
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config BR2_GCC_TARGET_ARCH
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string
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config BR2_GCC_TARGET_ABI
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string
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config BR2_GCC_TARGET_NAN
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string
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config BR2_GCC_TARGET_FP32_MODE
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string
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config BR2_GCC_TARGET_CPU
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string
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# The value of this option will be passed as --with-fpu=<value> when
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# building gcc (internal backend) or -mfpu=<value> in the toolchain
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# wrapper (external toolchain)
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config BR2_GCC_TARGET_FPU
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string
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# The value of this option will be passed as --with-float=<value> when
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# building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
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# wrapper (external toolchain)
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config BR2_GCC_TARGET_FLOAT_ABI
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string
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# The value of this option will be passed as --with-simd=<value> when
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# building gcc (internal backend) or -simd=<value> in the toolchain
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# wrapper (external toolchain)
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config BR2_GCC_TARGET_SIMD
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string
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# The value of this option will be passed as --with-mode=<value> when
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# building gcc (internal backend) or -m<value> in the toolchain
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# wrapper (external toolchain)
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config BR2_GCC_TARGET_MODE
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string
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# Must be selected by binary formats that support shared libraries.
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config BR2_BINFMT_SUPPORTS_SHARED
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bool
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# Must match the name of the architecture from readelf point of view,
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# i.e the "Machine:" field of readelf output. See get_machine_name()
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# in binutils/readelf.c for the list of possible values.
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config BR2_READELF_ARCH_NAME
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string
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if BR2_arcle
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source "arch/Config.in.arc"
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endif
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if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
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source "arch/Config.in.arm"
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endif
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if BR2_hppa
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source "arch/Config.in.hppa"
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endif
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if BR2_loongarch64
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source "arch/Config.in.loongarch"
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endif
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if BR2_m68k
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source "arch/Config.in.m68k"
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endif
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if BR2_microblazeel || BR2_microblazebe
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source "arch/Config.in.microblaze"
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endif
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if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
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source "arch/Config.in.mips"
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endif
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if BR2_or1k
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source "arch/Config.in.or1k"
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endif
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if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
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source "arch/Config.in.powerpc"
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endif
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if BR2_riscv
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source "arch/Config.in.riscv"
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endif
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if BR2_s390x
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source "arch/Config.in.s390x"
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endif
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if BR2_sh
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source "arch/Config.in.sh"
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endif
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if BR2_sparc || BR2_sparc64
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source "arch/Config.in.sparc"
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endif
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if BR2_i386 || BR2_x86_64
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source "arch/Config.in.x86"
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endif
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if BR2_xtensa
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source "arch/Config.in.xtensa"
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endif
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# Set up target binary format
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choice
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prompt "Target Binary Format"
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default BR2_BINFMT_ELF if BR2_USE_MMU
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default BR2_BINFMT_FLAT
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config BR2_BINFMT_ELF
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bool "ELF"
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depends on BR2_USE_MMU
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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ELF (Executable and Linkable Format) is a format for libraries
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and executables used across different architectures and
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operating systems.
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config BR2_BINFMT_FDPIC
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bool "FDPIC"
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depends on BR2_ARCH_HAS_FDPIC_SUPPORT
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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ELF FDPIC binaries are based on ELF, but allow the individual
|
|
load segments of a binary to be located in memory
|
|
independently of each other. This makes this format ideal for
|
|
use in environments where no MMU is available.
|
|
|
|
config BR2_BINFMT_FLAT
|
|
bool "FLAT"
|
|
depends on !BR2_USE_MMU
|
|
help
|
|
FLAT binary is a relatively simple and lightweight executable
|
|
format based on the original a.out format. It is widely used
|
|
in environment where no MMU is available.
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|
|
|
endchoice
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endmenu # Target options
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