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Those target configurations marked as "secondary" will be tested with a lower probability in autobuilders. The intent is to focus the Buildroot development (and bugfixes) on mainstream configurations, while still keeping some other, less common, configurations. This commit marks the following CPU architectures as secondary: BR2_arcle (ARC little endian) BR2_armeb (ARM big endian) BR2_aarch64_be (AArch64 big endian) BR2_hppa (PA-RISC) BR2_loongarch64 BR2_m68k BR2_microblazeel (Microblaze AXI, little endian) BR2_microblazebe (Microblaze non-AXI, big endian) BR2_mips (MIPS, big endian) BR2_mipsel (MIPS, little endian) BR2_mips64 (MIPS64 big endian) BR2_or1k (OpenRISC) BR2_powerpc (PowerPC, big endian) BR2_powerpc64 (PowerPC64, big endian) BR2_s390x BR2_sh (SuperH) BR2_sparc BR2_sparc64 BR2_xtensa In the following CPU architecture, only specific configurations are marked secondary: In BR2_armeb (ARM little endian), - armv4 cores (arm920t, arm922t, fa526/626, strongarm sa110/sa1100) In BR2_riscv: - all 32-bit configurations - 64-bit no-MMU In BR2_i386 (x86 32-bit), - i486, i586 and X1000 CPU There was no strict rule established to build this list of secondary configurations. This list was built mainly from the observation of which architecture/CPUs are still widely used in the field (disregarding its age), the quality of their upstream support and the general relevance in the Buildroot project. Signed-off-by: Julien Olivain <ju.o@free.fr> [Arnout: use !BR2_HIDE_SECONDARY_TARGET_OPTIONS instead of BR2_SHOW_SECONDARY_TARGET_OPTIONS] Signed-off-by: Arnout Vandecappelle <arnout@rnout.be>
136 lines
3.0 KiB
Plaintext
136 lines
3.0 KiB
Plaintext
# RISC-V CPU ISA extensions.
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choice
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prompt "Target Architecture Variant"
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default BR2_riscv_g
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config BR2_riscv_g
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bool "General purpose (G)"
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select BR2_RISCV_ISA_RVI
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select BR2_RISCV_ISA_RVM
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select BR2_RISCV_ISA_RVA
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select BR2_RISCV_ISA_RVF
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select BR2_RISCV_ISA_RVD
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help
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General purpose (G) is equivalent to IMAFD.
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config BR2_riscv_custom
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bool "Custom architecture"
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select BR2_RISCV_ISA_RVI
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endchoice
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comment "Instruction Set Extensions"
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config BR2_RISCV_ISA_RVI
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bool "Base Integer (I)"
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config BR2_RISCV_ISA_RVM
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bool "Integer Multiplication and Division (M)"
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config BR2_RISCV_ISA_RVA
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bool "Atomic Instructions (A)"
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config BR2_RISCV_ISA_RVF
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bool "Single-precision Floating-point (F)"
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config BR2_RISCV_ISA_RVD
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bool "Double-precision Floating-point (D)"
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depends on BR2_RISCV_ISA_RVF
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config BR2_RISCV_ISA_RVC
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bool "Compressed Instructions (C)"
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config BR2_RISCV_ISA_RVV
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bool "Vector Instructions (V)"
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
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config BR2_RISCV_ISA_EXTRA
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string "Append extra RISC-V ISA extensions"
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help
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Extra ISA extensions to append to the ISA extensions string.
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They are underscore-separated. For example,
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"zba_zbb_zvl256b".
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choice
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prompt "Target Architecture Size"
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default BR2_RISCV_64
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config BR2_RISCV_32
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bool "32-bit"
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depends on !BR2_HIDE_SECONDARY_TARGET_OPTIONS
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config BR2_RISCV_64
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bool "64-bit"
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select BR2_ARCH_IS_64
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select BR2_RISCV_USE_MMU if BR2_HIDE_SECONDARY_TARGET_OPTIONS
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endchoice
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config BR2_RISCV_USE_MMU
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bool "MMU support"
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default y
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select BR2_USE_MMU
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help
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Enable this option if your RISC-V core has a MMU (Memory
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Management Unit).
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choice
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prompt "Target ABI"
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default BR2_RISCV_ABI_ILP32D if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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default BR2_RISCV_ABI_ILP32F if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64
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default BR2_RISCV_ABI_LP64D if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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default BR2_RISCV_ABI_LP64F if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64
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config BR2_RISCV_ABI_ILP32
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bool "ilp32"
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depends on !BR2_ARCH_IS_64
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config BR2_RISCV_ABI_ILP32F
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bool "ilp32f"
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depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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config BR2_RISCV_ABI_ILP32D
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bool "ilp32d"
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depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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config BR2_RISCV_ABI_LP64
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bool "lp64"
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depends on BR2_ARCH_IS_64
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config BR2_RISCV_ABI_LP64F
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bool "lp64f"
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depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF
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depends on BR2_USE_MMU
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config BR2_RISCV_ABI_LP64D
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bool "lp64d"
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depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
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endchoice
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config BR2_ARCH
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default "riscv32" if !BR2_ARCH_IS_64
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default "riscv64" if BR2_ARCH_IS_64
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config BR2_NORMALIZED_ARCH
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default "riscv"
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config BR2_ENDIAN
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default "LITTLE"
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config BR2_GCC_TARGET_ABI
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default "ilp32" if BR2_RISCV_ABI_ILP32
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default "ilp32f" if BR2_RISCV_ABI_ILP32F
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default "ilp32d" if BR2_RISCV_ABI_ILP32D
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default "lp64" if BR2_RISCV_ABI_LP64
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default "lp64f" if BR2_RISCV_ABI_LP64F
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default "lp64d" if BR2_RISCV_ABI_LP64D
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config BR2_READELF_ARCH_NAME
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default "RISC-V"
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# vim: ft=kconfig
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# -*- mode:kconfig; -*-
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