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GP-7016: Corrected VPEXTRW to ignore the VEX.W1 bit

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ghidorahrex
2026-06-29 10:24:13 -04:00
parent 144d4a1b54
commit 6c1352fc90
1 changed files with 2 additions and 2 deletions
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4
Ghidra/Processors/x86/data/languages/avx.sinc
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@@ -1871,14 +1871,14 @@ define pcodeop vpextrq_avx ;
# PEXTRW 4-277 PAGE 1397 LINE 72478
define pcodeop vpextrw_avx ;
:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8
{
Reg32 = vpextrw_avx( XmmReg2, imm8:1 );
# TODO Reg64 = zext(Reg32)
}
# PEXTRW 4-277 PAGE 1397 LINE 72483
:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & Reg32_m16; imm8
{
Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 );
# TODO Reg64 = zext(Reg32)